How can I evaluate a bond wire's effect on high-speed signal integrity

Question

I am currently getting involved in one PCB design which is associated with high-speed signal(40Gbps PAM4 signal).On the board,a chip which transmits and receives data is bonded and transfers data through the traces and connectors.

I know signal running at such speed is susceptible to skin effect,dielectric loss and reflections.I have also heard bond wire should be as short as possible to reduce its inductance,so I try to place those pads(also known as gold fingers) of high-speed signal really close to the chip(as 7,8,13,14,17,18,20 shown in 1).

My questions are:

(1)Is the length of bond wire shorter,the better?What is the theoretical basis?

(2)Can I pick up the best bonding wire length based on simulation result?What simulation tool should I use?(HFSS,ADS maybe?)

(3)In some article,bond wire is treated as transmission line.But isn't this too short to be modeled as?Is this a good approximation?

(4)Except from bond wire length,what are the design considerations of pad(gold finger) size?

Any insightful answer of any one of the questions will be appreciated,thanks!

Answer 1

Is the length of bond wire shorter,the better?

In general, yes. However if the pad on the board or on the IC has excess capacitance, increasing the bondwire length might help to compensate for it.

Can I pick up the best bonding wire length based on simulation result?What simulation tool should I use?(HFSS,ADS maybe?)

Very crudely, you can model a bond wire as an inductor with 1 nH per mm of bond wire length.

If you have access to ADS, it does have some bond wire models that are more sophisticated. These will include effects from the shape of the bondwire loop and mutual inductance between neighboring wires. In my experience, though, it is not obvious what many of the parameters required for these models should be in any particular physical situation.

If you have access to HFSS, of course you can simply model the 3-d structure.

In some article,bonding wire is treated as transmission line.But isn't this too short to be modeled as?Is this a good approximation?

Conceivably, yes, but it's difficult to know where the return path is (if you don't know the details of the chip design) in order to work out the transmission line parameters. Doing so would likely require starting with HFSS or another 3-d FEM tool.

Except from bonding wire length,what are the design considerations of pad(gold finger) size?

Generally, the smaller the better to avoid excess capacitance. The minimum size will likely be determined by the capabilities of your PWB manufacturer and/or die-attach/wirebonding shop.

Looking at your layout, some of your pads might be too close to the chip. First, because you don't want the wirebonding tool to crash into the chip during wirebonding. Second because die-attach epoxy (assuming an epoxy process) might squeeze out from under the chip and cover those pads.