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I am currently getting involved in one PCB design which is associated with high-speed signal(40Gbps PAM4 signal).On the board,a chip which transmits and receives data is bonded and transfers data through the traces and connectors.

I know signal running at such speed is susceptible to skin effect,dielectric loss and reflections.I have also heard bond wire should be as short as possible to reduce its inductance,so I try to place those pads(also known as gold fingers) of high-speed signal really close to the chip(as 7,8,13,14,17,18,20 shown in 1).
enter image description here

My questions are:

(1)Is the length of bond wire shorter,the better?What is the theoretical basis?

(2)Can I pick up the best bonding wire length based on simulation result?What simulation tool should I use?(HFSS,ADS maybe?)

(3)In some article,bond wire is treated as transmission line.But isn't this too short to be modeled as?Is this a good approximation?

(4)Except from bond wire length,what are the design considerations of pad(gold finger) size?

Any insightful answer of any one of the questions will be appreciated,thanks!

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  • \$\begingroup\$ Why don't you simply measure the S-parameters of the bonded IC? You can also measure the bond wires when they are connected to an open circuit i.e. no IC. Also, at 40Gbps everything is a transmission line e.g. a via to an inner layer introduces an open stub because it goes all the way to the other side. Generally the bond wires need to be short, mainly because of losses and return path current loops. \$\endgroup\$
    – user110971
    Commented Nov 11, 2016 at 15:32
  • \$\begingroup\$ @user110971 Since I haven't got my wires bonded yet,what does measuring S-parameters mean?like modeling them as \$\endgroup\$
    – Xiao Xiang
    Commented Nov 12, 2016 at 1:34
  • \$\begingroup\$ using a network analyzer to measure the impedance. \$\endgroup\$
    – user110971
    Commented Nov 12, 2016 at 1:36
  • \$\begingroup\$ @user110971 A network analyzer in real world? That's a little bit hard to do at the moment,so can I just model them as transmission line based on their length and shape,and measure their S21&S11 in ADS?I've noticed in bethesignal.com/wp/… uses the microstrip model to evaluate the bond wire,is that the way you are talking about?As bond wire is halfway in the air,is that a good approximation? \$\endgroup\$
    – Xiao Xiang
    Commented Nov 12, 2016 at 1:52
  • \$\begingroup\$ Use HFSS if you have access to it \$\endgroup\$
    – Mike
    Commented Nov 12, 2016 at 7:58

1 Answer 1

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Is the length of bond wire shorter,the better?

In general, yes. However if the pad on the board or on the IC has excess capacitance, increasing the bondwire length might help to compensate for it.

Can I pick up the best bonding wire length based on simulation result?What simulation tool should I use?(HFSS,ADS maybe?)

Very crudely, you can model a bond wire as an inductor with 1 nH per mm of bond wire length.

If you have access to ADS, it does have some bond wire models that are more sophisticated. These will include effects from the shape of the bondwire loop and mutual inductance between neighboring wires. In my experience, though, it is not obvious what many of the parameters required for these models should be in any particular physical situation.

If you have access to HFSS, of course you can simply model the 3-d structure.

In some article,bonding wire is treated as transmission line.But isn't this too short to be modeled as?Is this a good approximation?

Conceivably, yes, but it's difficult to know where the return path is (if you don't know the details of the chip design) in order to work out the transmission line parameters. Doing so would likely require starting with HFSS or another 3-d FEM tool.

Except from bonding wire length,what are the design considerations of pad(gold finger) size?

Generally, the smaller the better to avoid excess capacitance. The minimum size will likely be determined by the capabilities of your PWB manufacturer and/or die-attach/wirebonding shop.

Looking at your layout, some of your pads might be too close to the chip. First, because you don't want the wirebonding tool to crash into the chip during wirebonding. Second because die-attach epoxy (assuming an epoxy process) might squeeze out from under the chip and cover those pads.

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  • \$\begingroup\$ An additional note. For high-speed signals, it may be advisable to use a conductive epoxy to bond the die to its pad. From my experience, the epoxy used can have an enormous effect on EMI at 100's of MHz. Which suggests that modeling at multiple GHz may be very challenging. \$\endgroup\$
    – user57037
    Commented Nov 11, 2016 at 17:16
  • \$\begingroup\$ @Photon (1)I've known there is a capacitance between the pad and ground plane below,is this the mainly excessive capacitance you are talking about?And compensation is in terms of impedance match,right? \$\endgroup\$
    – Xiao Xiang
    Commented Nov 12, 2016 at 2:01
  • \$\begingroup\$ @Photon (2)Now I just want to decide on how long bond wire should be used in terms of signal integrity,even very crudely.If I have already got the pad size and its distance to the ground plane so I can roughly estimate the capacitance,is the length mainly based on the impedance combined by the inductance it brings and the capacitance? \$\endgroup\$
    – Xiao Xiang
    Commented Nov 12, 2016 at 2:11
  • \$\begingroup\$ @mkeith could you go into some detail about the effect the epoxy brings about? \$\endgroup\$
    – Xiao Xiang
    Commented Nov 12, 2016 at 2:25
  • \$\begingroup\$ Well, this is based on one experience. It was a microprocessor IC die, attached directly to PCB and bonded out with 1 mil aluminum wire. The standard process was to use conductive epoxy (expensive). We experimented with a more standard epoxy, but the EMI performance was not very good, so we continued to use the conductive epoxy. The entire area where the die was placed was exposed GND pad. We had a GND ring just outside the die area where all GND bondwires attached to PCB. This was a 100 MHz 32 bit embedded processor. \$\endgroup\$
    – user57037
    Commented Nov 12, 2016 at 17:00

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