I'm given this configuration to solve for a IC-Timer 555 in astable mode to get a 50% duty cycle however I'm having some difficulties in the calculations.
The circuit is modified a bit as shown.
simulate this circuit – Schematic created using CircuitLab
So during a HIGH output, Discharge is open and the capacitor charges in time 0.69R2*C2.
However, during LOW output, R1 is also grounded. In this case I'm having difficulty calculating the time period. If I could get some help in calculating the Tlow and thus proving that the duty cycle is 50%, that would be a big help.
$$What I'm getting is, Voltage across capacitor(t)=[Vcc/Ra*C + 2Vcc/3]e^-(1/C(R1||R2)
Now, a t=Tlow I should have Voltage across the capacitor as Vcc/3. On solving this I get Tlow = (R1||R2)*C *ln((3+2R1*C)/R1*C))
My attempt at the solution:
Applying KCL at the common node:
\$(Vcc-Vc)/R2=Vc/Rb + C\$*dVc/dt\$\$
Taking Laplace transform (Initial condition: \$ Vc=2Vcc/3\$ and simplifying:
\$ Vcc[1/R1 + 2C/3] = Vc *[1/R1 + 1/R2 + sC]\$
on Rearranging: \$ \frac{Vcc(\frac{1}{R1} + \frac{2C}{3})}{(C*[\frac{1}{R1*C}+\frac{1}{R2*C}+s])}\$ = Vc
Taking inverse laplace transform, putting Vc=Vcc/3 for t=Tlow, I get the above answer. Please help me out.
I'm getting the correct answer by solving only in time domain, while I'm satisfied with that, I'd like to know what possible mistake am I making in the method using laplace transform?