Quick, and potentially silly question.
I'm working on an old board design (late 70's) that utilizes a 6800 processor. The current board design left a few address lines from the CPU unused. I'd like to utilize these in a new board design.
However, in order to do that, I need to introduce a CPLD between the CPU and ROM (EPROM). The CPU runs at 850khz, and while that's pretty slow, I figured that before I worried about programming a CPLD, I'd ask this -
Could a CPLD inline between the CPU and ROMs, adding between a 7ns and 25ns delay adversely affect the CPU running at that speed?
I want to say no, but thought I'd check.
Edit Notes: Bus speed should be the same - HOWEVER, a PIA interrupt is connected to a 555 timer that should run at 450khz, regardless of the CPU's frequency. The CPLD will be replacing the other logic gate chips, and be connected directly to the CPU address lines and the EPROMs address lines. So any delay would be limited to the CPLD, not added on to other logics. EPROM speeds will range between 70ns and 200ns. (My new design will allow the current 2732 EPROMs to be switched out with newer EPROMs and Flash chips. I guess the flash chips could be faster - but I doubt that would be an issue.) I unfortunately can't post a schematic, as I'm not finished with it yet. :)