Quick, and potentially silly question.

I'm working on an old board design (late 70's) that utilizes a 6800 processor. The current board design left a few address lines from the CPU unused. I'd like to utilize these in a new board design.

However, in order to do that, I need to introduce a CPLD between the CPU and ROM (EPROM). The CPU runs at 850khz, and while that's pretty slow, I figured that before I worried about programming a CPLD, I'd ask this -

Could a CPLD inline between the CPU and ROMs, adding between a 7ns and 25ns delay adversely affect the CPU running at that speed?

I want to say no, but thought I'd check.

Edit Notes: Bus speed should be the same - HOWEVER, a PIA interrupt is connected to a 555 timer that should run at 450khz, regardless of the CPU's frequency. The CPLD will be replacing the other logic gate chips, and be connected directly to the CPU address lines and the EPROMs address lines. So any delay would be limited to the CPLD, not added on to other logics. EPROM speeds will range between 70ns and 200ns. (My new design will allow the current 2732 EPROMs to be switched out with newer EPROMs and Flash chips. I guess the flash chips could be faster - but I doubt that would be an issue.) I unfortunately can't post a schematic, as I'm not finished with it yet. :)


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    \$\begingroup\$ Interesting would be at what frequency the bus to the ROM is operating. \$\endgroup\$ – Botnic Nov 11 '16 at 21:44
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    \$\begingroup\$ A 6800 runs at 2MHz maximum. Do you mean 850kHz? Kind of a big difference. If you look at the datasheets for CPU and memory you will find timing diagrams showing the relevant timing constraints. Chances are it's okay, assuming 0.85MHz but that's just a wild guess. \$\endgroup\$ – Spehro Pefhany Nov 11 '16 at 21:46
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    \$\begingroup\$ A 6800 might have used a 74LS138 (or other chips of that vintage) as an address decoder. The 74LS138 has propagation delays of 20 (typ) to 40 (max) nS, so there should be no problem with your CPLD. \$\endgroup\$ – Peter Bennett Nov 11 '16 at 22:18
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    \$\begingroup\$ Sorry guys, habit made me mistype the frequency. It is 850khz. Fixed the question. @PeterBennett - yes, there's up to three of various gate chips for inverting address lines depending on the chip being selected. I'll dig into see how fast the bus runs - off-hand from previous research, it may be running at around 450khz, but I'm not 100% on that. \$\endgroup\$ – Coyttl Nov 11 '16 at 23:12
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    \$\begingroup\$ Normally the bus runs at the same speed as the CPU. What speed is the EPROM? Will the CPLD be replacing existing logic, or added to it? Can you show us the schematic? \$\endgroup\$ – Bruce Abbott Nov 12 '16 at 2:54

Could a CPLD inline between the CPU and ROMs, adding between a 7ns and 25ns delay adversely affect the CPU running at that speed?

Almost certainly not. 25 ns (worst case) is roughly 2% of your system's cycle time. It's negligible.

Low clock frequencies (under 1 MHz) on older systems are often generated by RC oscillators. If your system is using one, it probably varies by at least 2% with temperature -- meaning that your system certainly has at least 25 ns of slack available.

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  • \$\begingroup\$ Going to go ahead and mark this as answer. Once I finish the new schematics and get a test boards made - I'll see if it works. :) If it doesn't, I'll update this post here. \$\endgroup\$ – Coyttl Nov 13 '16 at 19:52

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