Basically, I want to build a circuit that takes an input. When the input is 1, the circuit outputs a 1. However, on the next rising clock, it will output a 0 for the rest of the time, regardless of what the input is.

  • if input = 000000000100000, output = 000000000100000
  • if input = 011111, output = 010000
  • 1
    \$\begingroup\$ What clock rate and how many 0s? \$\endgroup\$
    – owg60
    Nov 13 '16 at 1:26
  • 1
    \$\begingroup\$ Look at a one shot. \$\endgroup\$
    – Matt Young
    Nov 13 '16 at 1:29
  • 3
    \$\begingroup\$ This is just a simple state machine. But do you ever want to reset it, so it can output a 1 again some time? Or should it latch back to zero forever? How would it get armed? With a button press, or digital input or do you want it to power-on in the armed state? \$\endgroup\$
    – mkeith
    Nov 13 '16 at 1:30
  • \$\begingroup\$ Or even a latched edge detector. \$\endgroup\$
    – Daniel
    Nov 13 '16 at 2:23
  • \$\begingroup\$ @Daniel, OP wants it to be high for not more than one clock period. So it needs to have at least one internal register so that it doesn't re-trigger. Also, I think the OP should design it so that it always stays high for at least one full clock period. Otherwise the pulse width will depend on the timing between the input edge and the clock. In some cases it might just barely glitch high and then turn off. \$\endgroup\$
    – mkeith
    Nov 13 '16 at 2:27

Is this the behavior you are after?

enter image description here

That assumes that the initial state of the flip flop is zero. Reset the flip-flop to '0' manually when you want to start again. You didn't state if the input signal was already synchronous with the clock domain: Add a couple meta-stability registers to the input if not.


I can't tell from your description what ends this sequence. I'm assuming that it would end at the next zero and repeat.


logic analyzer


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