# Creating a logic circuit with only NAND gates

I am supposed to make a logic circuit with only NAND gates.

I have created a truth table and i have extracted the boolean expression using a karnaugh map.

My function is: $\overline XZ + XY$

How can i draw this circuit using only 4 NAND gates?

UPDATE

**So this is how much is given from the teacher as to "start with" an I am supposed to draw the lines through this circuit of NAND gates to create the function ~xz + xy. I still get so confused when starting to draw the lines even though all the great help from all of you, I just cant make it to be in line with my function. It just seems hopeless.* *

As another UPDATE I added my karnaugh map to make sure with all of you that my function is correct.

• Look up de Morgan's rule – Andy aka Nov 13 '16 at 11:46
• Note that you can construct all other logic functions from NAND functions. One way is to make the gates you want from NANDs, then wire them up the way you conceptualize the solution. However, that my not yield the most efficient result. – Olin Lathrop Nov 13 '16 at 13:30
• Can you see that the answer I provided gives the circuit using four nand gates? I'm not sure what your question is. I gave you the answer. – owg60 Nov 16 '16 at 15:31

My function is: $\overline XZ + XY$

How can i draw this circuit using only NAND gates?

• X!Z+XY
• =((X)!Z)! . (XY)!)! de Morgan's
• = (((X)!.Z)! . (X.Y)!)! ( i did this on an iPad which is unable to drawing schematics)

simulate this circuit – Schematic created using CircuitLab

• thus for 3 inputs X,Y,Z
• using "!"= inverted output from NAND, a=b input
• "." = AND , "+" OR
• (NAND)x n = number of NAND-2in gates
• n = 4 pairs of parentheses.

And here is a NAND gate computer.

This is the answer to your problem. the gate that looks like an or gate is just another way to draw a nand gate.

De Morgan's theorem can get confusing. You have (A*B)' = A'+ B'. It may help to look at what this does to the schematic symbol. For the NAND gate it says change the symbol to an OR gate and move the bubbles to the input side. That being done, this circuit can be drawn;

Calling the output level the first level, you see this was done. Now since we have bubble on the outputs of the second level, they cancle out the input bubbles on the first level. So these three gates form a sum of products configuration and there was no need to use De Morgan on the whole function.

You pretty much had this on your third diagram. If instead of tying the inputs together at the second level you applied your four inputs, with X through and inverter, you would have gotten the answer.

• not X=X nand X
• X and Y=not(X nand Y)
• X or Y=(not X) nand (not Y)

I. e. ~XZ+XY=(((x nand x) nand z) nand ((x nand y) nand (x nand y)))

(Correct me if I am wrong).

• 6 NAND gates? hmm – Sunnyskyguy EE75 Nov 13 '16 at 16:43