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I would like to be able to view waveforms showing internal nodes in a circuit specified in Verilog in Altera Quartus Prime. I am having trouble doing so when a wire is an output of one module and an input of another. For example, my top-level entity includes:

module cpu(input [9:0] SW, output [9:0] LEDR);
    wire [7:0] pc_in;   
    wire [7:0] pc_out;  

    assign LEDR[7:0] = pc_out;

    pc my_pc(pc_in, SW[9], Continue, pc_out);     // pc_out is an output
    instruction_memory mem(pc_out, instruction);  // pc_out is an input
endmodule

(There's more, but I left out irrelevant parts.)

Here is the full definition of pc:

module pc(data, clock, enable, q);
    input [7:0] data;
    input clock;
    input enable;   
    output [7:0] q;  
    reg[7:0] q;

    always @ (posedge clock)
    begin
      if (enable)
          q <= data;
    end
endmodule

While I can find pc_out in the Node Finder and add it to my waveform in the Simulation Waveform Editor, it shows up as an input:

enter image description here

Note that it is logically equivalent to the LEDR output.

I tried changing the type of pc_out from INPUT to BIDIR, BURIED, COMB, OUTPUT, and REG, to no effect. (The only difference is the initial values.)

Whatever type value I set it to, that is how it appears in the output waveform shown after functional simulation: enter image description here

The same thing happens if I add the q output of my_pc (which is a basic register) and is equiavlent to pc_out.

I've successfully viewed signals by connecting them to outputs, but the chip I'm simulating only has 10 LEDs. (I'd be willing to switch to another real or fake chip with a huge number of outputs, if that's the best solution.)

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  • \$\begingroup\$ What does the interface to pc look like? In particular, what is the type of the second port (SW[9] in your code)? \$\endgroup\$
    – user39382
    Nov 14 '16 at 2:57
  • \$\begingroup\$ Thanks for looking at this, @duskwuff. I've added the contents of pc.v to the connection. I'm using SW[9] as a clock. \$\endgroup\$ Nov 14 '16 at 3:01
  • \$\begingroup\$ Is anything forcing Continue? \$\endgroup\$
    – user39382
    Nov 14 '16 at 3:05
  • \$\begingroup\$ @duskwuff Continue is sometimes low, sometimes high, as verified by a simulation with an LED assigned to it. The value of Continue is assigned a Boolean function of two other signals. \$\endgroup\$ Nov 14 '16 at 3:10
  • \$\begingroup\$ By what? There's nothing driving that signal in any of the code you've included. \$\endgroup\$
    – user39382
    Nov 14 '16 at 3:23

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