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One of my labs for my computer science hardware organization class has us designing a simple memory circuit. It uses RAM memory with 16 4-bit values. The description is as follows:

"Build a circuit in Logisim that writes the sequence of values 0x0 to 0xf to memory, as shown in Figure 2. The value 0x0 should first be written to the first memory location, then the value 0x1 to the second memory location, and so on. Your circuit should allow the user to reset the counters anytime (via a button). In addition, the circuit should stop writing values to memory after it has already written all memory locations exactly once."

My problem is with the final part, stopping the writing after all locations have been written. My circuit iterates through filling the sports 0x0 to 0xf but then continues and overwrites the current values due to the clock. I have provided a picture of my Logisim layout and I was hoping someone could help me fix this.

PartiallyCompletedRAM

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    \$\begingroup\$ One thing I think you'll find REALLY helps when you're asking for help is a neat and organized circuit. It also helps yourself with debugging. there are many places in this circuit that could be simplified, many wires that could be shortened. Its the same as when writing code, you have to create the circuit to be easy to read. For example, the clock signal on the right hand counter(?) could be shortened to one straight line. gates can be rearranged so there is a flow to them, a linearity. While I want to help, it is much more difficult to help when I have to work to know what is going on. \$\endgroup\$
    – ambitiose_sed_ineptum
    Commented Nov 15, 2016 at 22:39
  • \$\begingroup\$ @ambitiose_sed_ineptum alright I'll work on straightening it out. You're right that it's somewhat unclear where the wires are going \$\endgroup\$
    – paranoidandroid81
    Commented Nov 15, 2016 at 22:40
  • \$\begingroup\$ Are the AND gates at the bottom, leading to the inverter and the sel line an attempt at solving this problem? \$\endgroup\$
    – ambitiose_sed_ineptum
    Commented Nov 15, 2016 at 23:03
  • \$\begingroup\$ Yes they were meant to compare the counters for address and values. When they were equal, that would indicate that the max value has been reached and a 0 would be sent to sel, telling the chip to stop. \$\endgroup\$
    – paranoidandroid81
    Commented Nov 15, 2016 at 23:08
  • \$\begingroup\$ you shouldn't need the data AND gate to do this, just the ADDRESS line. But that wouldn't mess it up, what would is that those signals are ANDed with the clock, which makes the turn off signal dependent on the clock signal as well as the data and address signals. (Where turn off signal refers to the select line for the RAM module) \$\endgroup\$
    – ambitiose_sed_ineptum
    Commented Nov 15, 2016 at 23:12

1 Answer 1

Reset to default
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You need to use the ld port at the bottom of the RAM element. Tying it to 0 makes the RAM always try to perform a write -- to perform a read, ld needs to be high.

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  • \$\begingroup\$ OK thank you I'll trying having the ld port switch to 1 at the end. \$\endgroup\$
    – paranoidandroid81
    Commented Nov 15, 2016 at 23:12
  • \$\begingroup\$ I've connected the output of the AND gate to the ld port instead of the sel. The problem now is all values will load except the last "f" as the RAM changes to read mode before it is written. Not sure how to fix this. \$\endgroup\$
    – paranoidandroid81
    Commented Nov 15, 2016 at 23:22
  • \$\begingroup\$ I've uploaded a picture of what I've changed. \$\endgroup\$
    – paranoidandroid81
    Commented Nov 15, 2016 at 23:23

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