A well-designed CMOS inverter, therefore, has a low output impedance, which makes it less sensitive to noise and disturbances.

How can we say that a well designed inverter i.e with proper noise margin have low output impedance or vice versa?

  • \$\begingroup\$ what do you think? have you heard of shoot-thru? and how they avoid it \$\endgroup\$ Nov 16, 2016 at 5:09
  • \$\begingroup\$ So the cmos inverter avoids swithching on both transistors at the same time i.e when nmos is ON, pmos would be OFF and vice cersa, which would avoid forming a connection between VDD and ground. Is that what you mean by avoiding shoot-through? \$\endgroup\$
    – HWDesigner
    Nov 16, 2016 at 5:21
  • \$\begingroup\$ What is the signal size and impedance of potential noise sources relative to the node in question? \$\endgroup\$
    – Andy aka
    Nov 16, 2016 at 9:31
  • \$\begingroup\$ NO actually both FETS are in saturation mode at Vout=Vcc/2 but the Vgs RdsOn characteristics give a fairly flat characteristic. This varies with Vcc, T and logic family. Historically this std design has migrated from 300~1k for CD4xxx series to 22~33 Ohms for 3V logic 74ALCxx. This can be examined by Vol/Iol or (Vcc-Voh)/Ioh at various Vcc values \$\endgroup\$ Nov 16, 2016 at 12:37
  • \$\begingroup\$ thus you see the Pd in the output stage defines the design of each P/Nch driver RdsOn vs Vcc max for each family. Lower Vcc max implies the IC design can have lower RdsOn. But while impredance drops, so too does the Voltage margin from Vth_in and each rail. Thus the change in impedance of driver as logic families go towards lower Vcc (min:max) the Zout MUST go lower to maintain the same immunity to stray "reactance" with large swings e.g. 1kV arc via 1 pF stray with xx dv/dt or 10Amp step from xx nH stray Lat V=LdI/dt for noise and Z ratio = atten. of glitch - Vcc/2=margin \$\endgroup\$ Nov 16, 2016 at 12:53

1 Answer 1


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This typical MOSFET is intended to demonstrate the characteristics similar to 74HCxx family logic with a complementary Pch being the inverse such that the admittances add then inverted to define the Zout where nominal at 4.5V is near 50 Ohms. and at Vcc/2 is slightly higher.

  • Thus there is a wide margin but it is well controlled to prevent shoot-thru.
  • Also when self biased when Vout=Vcc/2 with no input as a linear amplifier ac coupled, the power drain is not excessive.

  • This ignores the substrate PNPN structure that causes latchup if Vin goes outside the supply rail by 0.6V but internally clamped by 2 stage ESD diodes with 10k in series limited to 5mA by diode ESR, which I have documented on this site.

  • Historically this std design has migrated from 300~1kOhm for CD4xxx series used from 15V-3V then for 3V logic 74ALCxx, Zout is 22~33 Ohms @25'C .
    • This can be examined by Vol/Iol or (Vcc-Voh)/Ioh at various Vcc values to be consistent across most logic devices in same family and all suppliers
    • e.g. 74S,74HC,74AL, etc and 50 more different CMOS families all have similar Zouts that are dependent on the max Vcc spec but with smaller lithography and lower rise times possible with lower input capacitance gives improve transition speed as well as similar Noise margin.
    • when noise margin is inadequate Schmitt Input NAND Gates or Inverters are chosen which have ~ 50 % input hysteresis

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