Some FPGAs have both DCM (Digital Clock Manager) and PLL (Phase Lock Loop) for use in internal clock generation.
Xilinx Spartan-6 FPGA Clocking Resources UG382 (v1.10) documentation describes a number of features for DCM:
- Eliminate clock skew
- Phase shift a clock signal
- Multiply or divide an incoming clock frequency or synthesize a completely new
- Condition a clock, ensuring a clean output clock with a 50% duty cycle
- Mirror, forward, or rebuffer a clock signal
- Clock input jitter filtering
- Free-running oscillator
- Spread-spectrum clock generation
However, to my understanding all these (or at least the majority, maybe not the "Free-running oscillator") are also available when using a PLL.
So, what is the difference in using a DCM vs. a PLL in an FPGA design?