Some FPGAs have both DCM (Digital Clock Manager) and PLL (Phase Lock Loop) for use in internal clock generation.

Xilinx Spartan-6 FPGA Clocking Resources UG382 (v1.10) documentation describes a number of features for DCM:

  • Eliminate clock skew
  • Phase shift a clock signal
  • Multiply or divide an incoming clock frequency or synthesize a completely new
  • Condition a clock, ensuring a clean output clock with a 50% duty cycle
  • Mirror, forward, or rebuffer a clock signal
  • Clock input jitter filtering
  • Free-running oscillator
  • Spread-spectrum clock generation

However, to my understanding all these (or at least the majority, maybe not the "Free-running oscillator") are also available when using a PLL.

So, what is the difference in using a DCM vs. a PLL in an FPGA design?


2 Answers 2


Xilinx use the term DCM for their enhancement to what they used to call a DLL, or Delay Locked Loop.

This (DLL) was a tapped delay line fed from the original clock signal, by selecting different taps, you could get different delays on the output clock signal. As the delays are unpredictable, logic compared the outputs from different taps until it found which tap number gave a full clock cycle delay - it was "unlocked" until it found the right tap. Then it updated that tap number as the delays drifted (e.g. as the input frequency changed or the chip warmed up) then other delays (e.g. 90 degrees, 180 degrees, were computed from that.

So it provided vaguely PLL-like behaviour without any analog circuitry, which was difficult to achieve in their processes at the time. Downside was that the jitter spectrum was different from a PLL as the delay was always an integral number of taps.

If you cascaded DLLs or DCMs, the second one will probably work, but a third one may have dificulty locking up due to the jitter imposed by the others.

The DCM is based on the same idea but provides other functionality such as clock frequency multiplication.

Newer FPGAs offer both DCM (DLL) and PLL but I expect the DCM is still easier to produce.

  • 1
    \$\begingroup\$ Thanks for the detailed technical description; that is very useful to understanding the technology and uses. Are there any situations where DCM should be used instead of PLL, or vice versa, or is it more a question about use the one where e.g. jitter and freq. will ensure timing closure? \$\endgroup\$
    – EquipDev
    Commented Nov 16, 2016 at 10:34
  • \$\begingroup\$ Well, if you need jitter attenuation or you need to track a varying clock, you need the PLL. Also, DCMs usually have a low frequency limit (where the one cycle delay falls off the end of the delay line!) so slow clocks need a PLL. General rule is, use the DCM where it'll do the job, use PLL where you need it. \$\endgroup\$
    – user16324
    Commented Nov 16, 2016 at 10:41
  • \$\begingroup\$ Thanks, very useful, and great rule to use the cheap resources (DCM) first where possible, and then the more expensive and versatile (PLL) is required. \$\endgroup\$
    – EquipDev
    Commented Nov 16, 2016 at 11:09

So, first of all, how an FPGA manufacturer decides to name components is mainly a marketing choice. So there's no inherent significance in that. It's always good to remember.

Then: a PLL is really just that, a control loop in which the observed/corrected quantity is the phase (or a derivative of that) of a signal. Thus, it's a part of something that might generate clocks, but not the complete clock generator. Of course, it's like "transistor" used to stand for small radio receivers in the 1960's and 70's, because the central component was a transistor. But a transistor alone doesn't make a radio receiver.

So, whatever is called PLL in your design needs to come with a description of what it actually does. Compare that description to the description of what a DCM does. That's the best answer we can give – "PLL", again, just actually means a single control loop, not a clock generator.

  • 3
    \$\begingroup\$ Thanks for the reply. However, my understanding is that this is more than a marketing naming game, since the Xilinx Spartan-6 has both DCMs and PLLs available. So for this reason, it is probably important to understand the difference, since there may be a good reason for the engineers to implement two different components that may at first glance look like providing similar functionality. \$\endgroup\$
    – EquipDev
    Commented Nov 16, 2016 at 9:24
  • \$\begingroup\$ As I said, it is a marketing name. No discussion necessary. A PLL is just a control loop. \$\endgroup\$ Commented Nov 16, 2016 at 9:33
  • 1
    \$\begingroup\$ @MarcusMüller Let's put OP's question differently: in which specific cases should you decide to use a DCM resource vs a PLL resource within the Spartan 6 FPGA (since it has both available)? You don't address this. PLL and DCM may be marketing names, but they both identify different actual blocks available in this FPGA, so they indeed probably have slightly different typical usages. \$\endgroup\$
    – dim
    Commented Nov 16, 2016 at 9:53
  • \$\begingroup\$ @dim but putting the question like that, one would have to ask "for what purpose?", lest OP's question remains unclear. In that case, I took the part of the question that is possible to answer, and explained how to answer the usage question (by comparing specs) himself/herself. \$\endgroup\$ Commented Nov 16, 2016 at 9:59
  • 1
    \$\begingroup\$ @dim stubbornness is one of the strengths commonly found in EEs :) But nevertheless, I can see your point. My problem really is that the document OP links to is a 116p explanation of the clocking ressources on the FPGAs - there's separate chapters that highlight what the DCM and the PLL modules, respectively, do. I can't copy & paste 20p of Xilinx Documentation – so lest OP specifies what she/he needs to do, I'm all out of ideas how to answer the question. \$\endgroup\$ Commented Nov 16, 2016 at 10:25

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