I was able to find the period without the diodes which was T=2RCln(3)

But I am unable to find the expression when we connect the two diodes. (Our course says it is : T= RCln( (VDD+Vd) /vt). I am unable to find out how we obtained this expression)

This is the circuit: astable multivibrator with limiting diodes

Please explain how to get the expression of the period of this circuit, and thank you.

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This is how it works. (even though I disagree with this academic example) 2nd stage pumps max current into diode, while saturated and charges cap so input reaches Vdd+Vf, ( depending on diode and ESR of CMOS family) then diode turns off and decays by natural logarithm to threshold \$v_t\$ ( exponential decay) thus the half period becomes...

\$\frac{1}{2}* \frac{1}{f} =T\$ (=7.87us in my simulation)

\$T= RC*ln((V_{DD}+V_f) /v_t)\$

thus 100k*100e-12*ln((5+0.579V)/2.5V)= 8.03us with an discrepancy of 1.6% enter image description here

Note the diodes I modeled here drop 580mV with 30mA spikes which can be a source of error as well as Vt and component tolerances.

Other details

The assumptions behind this model are flawed in so many ways, in reality with SCR Latchup effects if you exceed the absolute max input voltage. (Vss+0.5 and Vcc-0.5V) which is added for some ESD protection. I think they should ban this design for reasons of ESD diode stress, EMI egress, potential CMOS latchup and spurious oscillations on faster devices, , but don't sweat it

The actual CMOS devices come with Schottky diodes in two stages . They must be small to have react fast so they are all rated for 5mA max which is less than the drive current possible for some CMOS drivers. So this circuit is poor design to follow, but can be improved to protect ESD diodes or add much bigger Schottky diodes. But then this is not very efficient and causes large current spikes)

enter image description here I had to add 50R output to simulate 74HC gate output impedance and add 50pF to prevent spurious oscillation just before toggle.

But to analyze the circuit , looks at the differentiate pulse which decays to Vcc/2 then toggles polarity. So the Peak Voltage at the input of 1st gate (in simple theory) is Vf+Vdd and thus this decays to Vdd/2 for the Time constant From my experience , I can ballpark estimate the ESR of any forward diode such that if it is rated for 5mA @0.5V ( the absolute max outside Vdd,Vss before latchup will occur) this is equivalent to an ESR of <=100 Ohms at rated current.

Thus in my simulation with 100pF cap and 50R ESR and 100R diode the Cap "dv/dt" charge time current spike is 15 ns wide with 2~3ns rise time. ( which spews spectrum from clock rate up to 1/15ns=66Mhz and then harmonics above that to 1/(2~3ns)= 333MHz to 500MHz.. Nasty crosstalk....

Some diodes in newer devices may be rated for 20mA steady absolute max.

A simpler circuit uses a Schmitt gate Inv or NAND with 1 gate and a feedback R and C input to gnd with a triangle wave on input from 1/3 to 2/3 Vdd instead of a differentiated diode clipped signal decaying across Vdd/2 +/- 30% over temp

enter image description here

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  • \$\begingroup\$ Thank you for your explaination. I understand how it works (but not in the very deep details of its design) , but my problem is with finding the period of the wave when the diodes are connected. \$\endgroup\$ – Movsac Nov 16 '16 at 21:07
  • \$\begingroup\$ In Theory we say RC=T and Vout=63% of Vin for the exponential response. But here the step input only has to go to Vdd/2 to toggle but starts from a diode clamped overshoot of Vdd+Vf so if Vdd=5V and Vf=0.7V ask yourself what is the time for a 5V+0.7V pulse to droop towards 0 but switch at 2.5V for the half period. so Step in=5.7 and (5.7-2.5)/5.7=56% of voltage scale when the CMOS input theoretically switches at room temp. is pretty close to 63% = (e-1)/e ( or \$ln\$ to interpolate to 69%) \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 16 '16 at 21:50

Let's put some numbers in and see if that helps you. Assume Vdd=5 and Vd=0.7. Without the diodes, if Vo2 had just gone low the capacitor will start charging until it has 2.5V across it. This will cause Vo2 to go high and the opposite end will go Vdd+2.5=7.5V. It will start to discharge from there. Now it we include the diode to VDD something different happens. The diode be forward biased when Vo2 goes high and conduct a lot of current. It will do this until it turns off at Vdd+Vd or 5.7V. So now your capacitor is starting to discharge at 5.7 instead of 7.5. Do you see it?

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  • \$\begingroup\$ Thanks to you, I was able to reach the same formula in the course, but that was under the assumption that the diode does not turn off for the entire discharging period. Is that assumption viable? \$\endgroup\$ – Movsac Nov 16 '16 at 20:59
  • \$\begingroup\$ The diode turns off when Vin is within supply rail which happens pretty fast with a large narrow spike due to Zout usually<50 Ohms spewing EMI at the fastest dI/dt of the device. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 16 '16 at 21:20

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