I have a Problem with an LTspice simulation. Specifically, I am designing an 12V bridge amplifier. The Problem in my simulation is that there is an DC offset which partially defies logic as far as I can tell. I attached a screenshot of the schematic for reference. Please Note that this is a first draft!

LTspice schematic

As you can see, there is an 700 and then some mV DC Offset at the Inputs of the LTC6248 OP amps, behind the decoupling capacitors C1/2 at the outputs of the LT1994, which should not be there as far as I can tell. The capacitor should block all DC parts from U1 and the inputs of U2/3 should not generate a Voltege that large (thinking about the opamps dc offset here...)

The problem occurs with LTspiceIV and XVII,which are very picky as of late (XIIV in general, has anyone else trouble with LTspice as of late?) and also with different opamps and with ideal op`s. All models are from Linear and came with LTspice, no 3rd party libs used. So I am at a loss here and hope that anyone has an Idea where the DC offset comes from.

  • \$\begingroup\$ Too small to read \$\endgroup\$
    – Andy aka
    Nov 16 '16 at 21:23
  • \$\begingroup\$ Changed the picture, better now? \$\endgroup\$
    – Sarge
    Nov 16 '16 at 21:28
  • \$\begingroup\$ I know I'm late to the party, but the OP directives don't show what you think they do: they show the DC component at time t=0, at the beginning of the simulation. Unless the circuit has been solved, or you haven't loaded other .OP, it will only show the initial DC prior to any transients in the circuit. Also, the answers you got are valid, but in this case, the model of the opamps include an input resistance. \$\endgroup\$ Apr 10 '18 at 14:50

You need resistors to ground on these inputs to keep the input dc bias from just charging up the capacitors. In other words it's bad design and won't work.

They may be limiting at 0.7 volts because the model has internal protection diodes in place. See note 2 in the data sheet: -

Note 2: The inputs are protected by back-to-back diodes.

This means that if the inverting input is at 0V then the non-inverting input is clamped one diode drop higher.


Andy aka is on the right track, but your circuit is in very bad shape.

First, there is no need to establish a virtual ground for the Vcm of the input amp. A simple capacitor to ground will do.

Second, although you have accounted for input offset voltages on the LTC6248s, you have not considered input bias currents. With nowhere for that current to go it is charging up the inputs. A 0.75 volt level is apparently an artifact of the specifics of the amp model, although I would not expect a positive output to be produced by output protection. A DC bypass is required, as Andy says, but it must not be to ground. If this happens, negative cycles of the waveform will cause the 6248 inputs to go negative, and in your single-supply setup this is unacceptable. Here is where you need to generate a Vs/2 voltage, and connect the resistors to this point.

Finally, your buffers will not work as you think. With a Vgs(th) of 4 volts maximum, you will have an 8-volt dead zone at the buffer input, assuming that your Vs is large enough to accomodate this. Even if it does, when you include the MOSFET input capacitances you'll find that the closed loop will oscillate like crazy, with no obvious solution.

EDIT - The buffer topology you have chose is intended for use in digital outputs, especially as power MOSFET drivers for switching applications. It is not remotely OK for analog applications.


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