Passively Buffer Voltage

I am working on a project where I would like to use a single pole rotary switch as a mode switch, but also provide power to the MCU. By providing the common on the switch with 3V, I can identify what mode the switch is in at anytime by reading pins 1-4 on the MCU. Assuming an ideal op amp, one could simply buffer each rotary switch output and then combine the output of all buffers and connect them to the 3V input of the MCU. I would however prefer to use a passive solution to buffer each switch output rather than a active solution like the op amps. To formalize the question: Is there a way to passively buffer voltage? I don't consider myself a hardware wizard, so any suggestions are welcome.

UPDATE 11/19/2016: So I am trying to implement the circuit (see above) that Majenko suggested. I am simulating the load of an MCU with the 150 ohm resistor, and I made rough guess for the value of the other resistors (100k and 1k). The 2.2uF cap on the output is to account for the break before make nature of the rotary switch. In actual implementation, the 3V soruce will be a CR123 battery. Also note that in this circuit I only accounted for one mode. Imagine expanding this circuit to have multiple modes each with an additional NPN BJTs that all connect to the single PNP transistor base. Can you see anything wrong with this circuit? Is there a good way to decrease the total current needed to drive the BJTs?

• Would you consider a MOSFET too active for you? Nov 17, 2016 at 1:09
• To clarify your needs define Vin, I out, Zout other than monitor. So far it looks like a Quad Analog or a rotary switch that needs no buffering at all. Nov 17, 2016 at 1:12
• I knew it wouldn't be long before someone suggested that :). I would consider using MOSFETs, but wanted to see if someone could offer a truly passive solution first. The project is under serious power constraints, so I am always looking for passive ways to do things. Nov 17, 2016 at 1:12
• a "zero ohm" mechanical switch from a Voltage source does not need a buffer! What did you mean? isolation? filter? current limiter? power switch? Nov 17, 2016 at 1:13
• @TonyStewart.EEsince'75 I would suspect isolation of the switch positions from each other whilst having a common power control that is linked to all the switches. I am just drawing a MOSFET based answer right now. Nov 17, 2016 at 1:16

A simple high-side MOSFET switch (P channel) which is switched by multiple (wired OR) N-channel MOSFETs, should do the trick:

simulate this circuit – Schematic created using CircuitLab

The P-FET is normally off (R1 sees to that). When the switch is in a position to power either of the N-FETs (only 2 shown here - OFF position not shown - just add more in the same way for other positions on your switch (CircuitLab only has DPST)) then it pulls the gate of the P-FET low turning it on.

That gives you full isolation of all the switch positions from each other, low power consumption (near zero when off, and tiny amounts when on - the biggest drain is R1 - you can increase that up to 1MΩ if you like, though it will slow down the switch-off of the P-FET somewhat).

C1 is just a big reservoir to stop the MCU blacking out when you switch the switch to a new position (break-before-make = interruption in power).

When choosing your MOSFETs make sure the $R_{DSON}$ of the P FET is nice and low (the N FETs don't matter much) and be sure the threshold voltage ($V_{GS}$) of all of them is no more than around half your supply voltage (1.5V) to ensure good saturation.

• Thanks for the help, as well as taking the time to scheme it for me. Of all hardware, designing with FETS intimidates me most. Do you have a practical source you go to for more on designing with FETS rather than the theory of operation? Thanks again. Nov 17, 2016 at 1:55
• There are two ways of designing with FETs, just like with BJTs - easy and hard. Tbe hard way is when you are using them for linear amplification and such. That gets tricky. In this design they are simply switches. That's the easy way of working with them. There isn't much to designing with them like that. Either they are on or they are off and you don't care much about the fiddly bits in between. Nov 17, 2016 at 1:58
• Consider Logic Level FET can be used as Voltage controlled resistance with millions of options . You decide logic level control voltage, Switch resistance or RdsOn at some Vgs, high side or low side operation. All switches are inverting output so Pch are high side with active gate pull down for high side switch and Nch are Low side with pullup. Consider the source and load delta V and ESR to determine the current flow, All FETs have a transition charge capacitance (nF) that affects rise time which is inverse to RdsOn. Nov 17, 2016 at 1:59
• Why not put C1 across the N-FETs? Then you won't need as big of a capacitor. Jan 24, 2018 at 1:12

One way of solving the problem is to replace the opamps in your drawing with diodes.

The MCU will be fed with the largest voltage from the input wires.

There will be a voltage drop across the diodes so the MCU will be fed with a slightly less voltage. If you use shottkey diode will only cause about 0.3V drop and will probably be acceptable.

As the switch is rotated the voltage to the MCU may drop when it is between between positions. You will probably need a fairy large capacitor at the output (e.g. 100uF) so the voltage does not drop. You will also need to ensure your MCU starts up correctly as the supply voltage comes and goes.