Preparing a lab excercise, where we are tasked to generate a 1 Hz clock out of the 50 Mhz system clock of a FPGA. This should be achieved without using any libraries besides ieee.std_logic_1164 and ieee.numeric_std.
The obvious possibility would be, to run a counter. When it hits 25*10^6 ticks, a edge can be transmitted (alternating between rising and falling edged). Then reset the timer. This would require a 25 Bit timer and a 25 bit comparison. As our overall excercise is not that complex, we should not run into limitations of the FPGA ressources. However I wondered how this could be implemented more efficiently. E.g. one could compare only the first couple of bits thereby loosing accuracy of the clock frequency.
The excercise documentation notes, that such timers are usually only loocking at one bit within the counter. So one possibility would be to count faster, so that after half a second one specific bit would swap. This could be done by counting to 2^n and increasing the counter steps. However this would create an error due to the truncated remainder in the step size. E.g. counting to 2^30 with a step size of 43 would result in an error of 0.1% , whereas counting to 2^27 has an error of 6.9% with a step size of 5.
Are there more ressource efficient concepts to generate such a clock? Preferably using a counter and loocking at a single bit for clock generation.