I'm trying to write a Verilog code using a module in a .lib file, and compile the code using Synopsys design compiler. I compiled a memory module using my memory compiler, and it produced a .lib file. I think it contains a compiled memory module, but I cannot find how to use it in my Verilog code.

Using an analogy with C/C++, I think the .lib file is supposed to have something like a header file, so that I can include the header and use the module in my Verilog code. But it seems like that the .lib file don't have such header. Could anyone explain how to write a Verilog code using library modules?

  • \$\begingroup\$ I'd expect a memory compiler to produce .lib and .v as well as other files. Perhaps check if you skipped some optional step when you compiled the memory. \$\endgroup\$
    – HKOB
    May 18, 2019 at 13:18
  • \$\begingroup\$ How was the .lib of the module that you intend to use in your module generated? Was it written in VHDL/ Verilog? \$\endgroup\$ May 18, 2019 at 15:56

1 Answer 1


The .lib file is a timing model library file described in a Synopsys propietary language interpreted by Synopsys STA tool PrimeTime. You won't be able to use it to synthesize a design, you must use a .db file, which is a Synopsys proprietary binary format to describe library cells like your memory.

Check out the options of your memory generator software to write out a library file (not timing library file) in .db format.

  • \$\begingroup\$ No, .lib and .db file have the same information. A .db file is a .lib file in a compiled binary format so it is usually faster. \$\endgroup\$
    – HKOB
    May 18, 2019 at 13:22

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.