To generate FULL/EMPTY for FIFO control, the reading address/writing address needs to be transferred to the writing/reading side for comparison. A solution is to use gray code for the address to be safely delivered to the different clock domain because of only one bit will be flipped at a time. This is good if the depth of the FIFO D=2^K because only one bit changes for the transition from D-1 to 0. But what if D!=2^K, e.g., 13? The gray code is 1010 whereas the next address is 0000, for which 2 bits will be changed, and the 2-stage synchronizer is unsafe for such change. How is this problem solved for FIFOs with arbitrary depth? Will more complicated synchronization schemes be used? If yes, it seems converting from/to gray code is no longer necessary.
The physical size of the RAM used inside the FIFO must be a power of 2 for the gray code scheme to work. The maximum depth of the FIFO as seen by external logic can still be limited to something less than 2N, but the actual read and write address counters will run through the full range of 0 through 2N - 1.