I'm new to VHDL programming. I want to have frequency divider of an input clock signal by 2 consecutive integer x, y each of them last for 2 cycles. Actually I wrote it only for x. How can have clock cycle last for two periods? below is my code,thanks for your reply.
library ieee; use ieee.std_logic_1164.all; entity clk_divider is generic( x:integer:=2; y:integer:=3); port( clk_in:in std_logic; clk_out:out std_logic); end entity; architecture beh of clk_divider is begin process(clk_in) variable tmp:std_logic:='0'; variable count1:integer:=0; --variable count2:integer:=0; begin if (rising_edge(clk_in)) then count1:=count1+1; if(count1=x-1) then tmp:=not tmp; count1:=0; end if; end if; clk_out<=tmp; end process; end architecture;