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Update The circuit I used was wrong as answered, the output cap needs to be polarized in reverse from the drawing. It otherwises causes the DC bias!
Except that the cirucit is working fine, I am using it to power a raspberry PI audio from 1Vpp to 3Vpp

I have built a small audio amplifier to convert a 1vpp audio signal to 3vpp.
This signal is then fed into a strong amplifier with input impedance of around 6k.

The main signal I am going to drive is around 60Hz.

Here is the circuit I used as base: enter image description here

I left out the cap next to RB (maybe a mistake?), RL is 6K in my case.

At first I had big issues with this circuit, once I added 6k as RL the output signal broke down.
I changed the output capacitor from 0.1uF to around 4uF because it acted like a high pass filter and this seemed to have caused the voltage breakdown.

Now the voltage is mostly stable when I add RL (6k) but I have a DC offset at my audio output of about 2V.
The audio signal is looking perfect, 3Vpp but it's on +2V offset.

My guess: The Ra/Rb resistors are not perfect, so the middle voltage on + of the opamp is not perfectly centered, this causes the capacitor to be dragged up in voltage.
How can I get the signal cenetered around 0V and is my guess correct ?

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  • \$\begingroup\$ This circuit has a gain of 2, not 3 as you say you want. The gain of this circuit is R2/R1. \$\endgroup\$ – Olin Lathrop Nov 18 '16 at 12:07
  • \$\begingroup\$ Yes sure, the circuit is not identical with mine It's just the example I took from the interwebs :) The problem was the capacitor which I thought is unipolar but was polar and the wrong way around. I still have a slight DC offset now but just a small one \$\endgroup\$ – John Nov 18 '16 at 16:01
  • \$\begingroup\$ -1 for jerking us around with a schematic that doesn't represent what you are actually doing. \$\endgroup\$ – Olin Lathrop Nov 18 '16 at 16:22
  • \$\begingroup\$ You obviously did not understand the purpose of my question, actual values of R1 and R2 were irrelevant. -1 as much as you want, the question was already answered by someone who actually understood the issue :) \$\endgroup\$ – John Nov 18 '16 at 16:26
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TL;DR output C is the wrong way round

RA and RB set the +ve input voltage to 2.5v.

C1(series with R1) breaks the gain back to unity at DC, so the output will be centred around 2.5v DC.

C1(output cap) (see any problem with having the same C1 reference designator for several components?) should shift the output voltage to zero DC across RL (I assume RL will be in parallel with CL, see any problem with not showing all components on the schematic that are mentioned in the text?).

If you and I are using the same graphical convention, then C1output is a polarised capacitor, with the +ve terminal to the curved side (the symbol for a non-polar cap uses two straight lines). That means it is reverse biassed. A reverse biassed electrolytic will support a small voltage across it, perhaps half a volt, before the dielectric breaks down and it begins to conduct.

Your measurement of a 2v output offset is completely consistent with an average DC output from the amplifier of 2.5v, and only 0.5v across the capacitor.

BTW, the cap in series with R1 is the right way round. If the cap in shunt with RB is indeed polar, then it is reverse biassed, and if present would be expected to pull the voltage at that node down to less than vcc/2. However, at the value shown, it's more likely to be a non-polar capacitor, so will not disturb the voltage, regardless of how you've drawn it.

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  • \$\begingroup\$ The circuit is horrible, I appologize for having several similar named components :) It's not from me, I just found it. I am not sure if I could follow you on everything. I need the offset bias gone, how can I do that ? Should I use a polar or a unipolar cap at the end, does it matter (given that I fix the polarity) ? \$\endgroup\$ – John Nov 18 '16 at 11:41
  • \$\begingroup\$ omgosh! I got it. I did not even know about that capacitor behaviour when wrongly polarized. It seems to work :) thank you \$\endgroup\$ – John Nov 18 '16 at 11:49
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If you're using virtual ground (VGnd - Upper terminal of RB), that point should go to ground at the frequencies you're working at. That's why a capacitor is placed across RB. But it seems a 0.1nF = 100pF is quite low for this job. Try placing 10uF or higher.

Since the input (so the output) frequency is 60Hz, output coupling cap should be as large as possible (due to \$X_C=1/(2\pi f C)\$). By using 6k as the input impedance of the following stage and selecting the cut-off frequency as f(min)/2=30Hz, output coupling cap should be at least \$C_o=1/(2\pi \cdot 30 \cdot 6k) = 0.9\mu F\$. Try placing a 1uF non polarized cap.

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  • \$\begingroup\$ Why does the capacitor in parallel to Rb matter at all regarding to the frequencies I use ? I thought it is just there to remove ripple from the VCC line, I did not place that cap because I have no ripple on that VCC (it comes directly from a linear voltage reg circuit) My problem with the output cap is that when I increase it in size it creates the mentioned DC offset at the output \$\endgroup\$ – John Nov 18 '16 at 11:34
  • \$\begingroup\$ Since you're using single-supply config, you need to set the voltage at opamp's + terminal to Vcc/2 (called virtual ground) via RA and RB. Small signal analysis dictates us that virtual ground point should go to ground. But how? Via a large cap across RB. \$\endgroup\$ – Rohat Kılıç Nov 18 '16 at 11:48

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