The circuit I used was wrong as answered, the output cap needs to be polarized in reverse from the drawing. It otherwises causes the DC bias!
Except that the cirucit is working fine, I am using it to power a raspberry PI audio from 1Vpp to 3Vpp
I have built a small audio amplifier to convert a 1vpp audio signal to 3vpp.
This signal is then fed into a strong amplifier with input impedance of around 6k.
The main signal I am going to drive is around 60Hz.
I left out the cap next to RB (maybe a mistake?), RL is 6K in my case.
At first I had big issues with this circuit, once I added 6k as RL the output signal broke down.
I changed the output capacitor from 0.1uF to around 4uF because it acted like a high pass filter and this seemed to have caused the voltage breakdown.
Now the voltage is mostly stable when I add RL (6k) but I have a DC offset at my audio output of about 2V.
The audio signal is looking perfect, 3Vpp but it's on +2V offset.
My guess: The Ra/Rb resistors are not perfect, so the middle voltage on + of the opamp is not perfectly centered, this causes the capacitor to be dragged up in voltage.
How can I get the signal cenetered around 0V and is my guess correct ?