I've got a project in Altera's Quartus II software which is written in Verilog. I'm curious if anyone here has figured out how to export the Verilog as a gate level netlist. I'd like to simulate the design in Cadence. I'm interested in the spectral power draw of my design. Any tips, guys?
No, there's no way to export a gate-level netlist. Verilog simulators exist, and there are several compilers to intermediate levels, but the low-level mapping is all proprietary to each FPGA manufacturer: their tools divisions (think they) need to make money.
Even if you could, There's no way that Cadence (or any other circuit analysis tool) can analyze an FPGA design of any significant complexity. Even the simplest Cyclone II has 4,600 logic element blocks containing 16 logic functions, which probably represents 10,000,000 or more transistors. Then you've got 120kb of RAM, multipliers, peripherals, PLLs, etc. etc. etc. Even the simplest possible Verilog project will likely involve thousands of these transistors. Even with a big PC with lots of RAM, the simulation program isn't designed for this. A couple hundred transistors in a really complex design, maybe. Ten million? No way.
Cadence simulates a design at a device level: Each transistor is mapped as a transistor, with gate capacitance, leakage current, etc. For the FPGA, you don't need this level of detail. It's sufficient to model elements at a higher level than the device level. For this, Altera (and Xilinx, if you're on that platform) provide power estimators in their tools. As Brian pointed out, this is PowerPlay in Quartus. These tools take dynamic effects into account and have the transistor models already encoded.