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I have generated a VGA signal, and succeeded to draw a rectangle. I have also code for ROM designed using VHDL, and initialized with a file that has patterns. I'm beginner in VHDL and FPGA. I would like to read the contents of the ROM and use the VGA generator to display the contents.

here are the codes.

 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 ------------------------------------------------------------------
 ENTITY rom IS
 PORT (address: IN INTEGER RANGE 0 TO 15;
 data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
 END rom;
 ------------------------------------------------------------------
 ARCHITECTURE rom OF rom IS
 SIGNAL reg_address: INTEGER RANGE 0 TO 15;
 TYPE memory IS ARRAY (0 TO 15) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
 SIGNAL myrom: memory;
 ATTRIBUTE ram_init_file: STRING;
 ATTRIBUTE ram_init_file OF myrom: SIGNAL IS "rom_contents.mif";
 BEGIN
 data_out <= myrom(address);
 END rom;

VGA Generator Code

architecture Behavioral of VGA_display is   
    -- Intermediate register telling the exact position on display on screen.
    signal x : integer range 0 to 1023 := 100;
    signal y : integer range 0 to 1023 := 80;
begin
 -- On every positive edge of the clock counter condition is checked,
  output1: process(clock)
  begin
    if rising_edge (clock) then
        -- If the counter satisfy the condition, then output the colour that should appear.
        if (hcounter >= 1)  and (hcounter < 120) and (vcounter >= 1) and (vcounter < 120
                   ) then
          pixels <= x"F0";                  
        -- If the condition is not satisfied then the output colour will be black.
        else 
          pixels <= x"00";
        end if;
      end if;
   end process;
end Behavioral;

Currently I'm getting that from simulation result. enter image description here

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closed as unclear what you're asking by Chris Stratton, Voltage Spike, ThreePhaseEel, Daniel Grillo, Dmitry Grigoryev Nov 22 '16 at 15:19

Please clarify your specific problem or add additional details to highlight exactly what you need. As it's currently written, it’s hard to tell exactly what you're asking. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

  • \$\begingroup\$ You must state a specific, answerable question - it is not enough to merely state your general goal and post code. \$\endgroup\$ – Chris Stratton Nov 18 '16 at 17:03
  • \$\begingroup\$ @ChrisStratton I'm missing the link between the ROM and VGA generator. I don't know how to read the ROM then assign the values that I read to the VGA RGB generator. \$\endgroup\$ – Ahmed Saleh Nov 18 '16 at 17:03
  • \$\begingroup\$ How to bind the address to the pixel in VHDL that's my problem \$\endgroup\$ – Ahmed Saleh Nov 18 '16 at 17:21
  • \$\begingroup\$ Since they are clean powers of two, presumably merge your X and Y addresses to form a wider word (traditionally low bits from X, high bits from Y) and use that as a memory address. There have been many such projects published, reading the code of a few will probably be more informative than asking questions. Typically you want the output port width of your memory (something configurable on the majority of FPGAs) to match the bits per pixel (while the input width matches whatever you use as a data source), otherwise you'll need a shift register to turn words into pixels. \$\endgroup\$ – Chris Stratton Nov 18 '16 at 17:36
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    \$\begingroup\$ I'm not going to play "20 questions" with you. Obviously, you know how to make a region of the screen into a particular color. Creating N regions and making each one's color contingent on the value of a particular ROM bit is a straightforward mapping process. \$\endgroup\$ – Dave Tweed Nov 18 '16 at 21:09
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I have not written in VHDL for a long time but what you need to do would be something like this.

Instantiate the rom and connect the signals, e.g.

rom1: rom port map(address => addr, data_out => pix);

Somewhere appropriate, you assign the address by flattening the horizontal and vertical counts:

addr <= vcounter * 120 + hcounter;

This is likely to have type checking issue with VHDL as is. With this you would be relying on the synthesizer to optimize the x120 and add operation. I would waste 8 bytes/words to make each horizontal line occupies a power of 2 (=128) number of words, then I would write this in bit-slice operations and this would be a lot more efficient.

Finally, use the output pix inside your VGA_display block, such as:

pixels <= pix;
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  • \$\begingroup\$ Thanks man I got it. I tried your code, but it shows blank. here is the code that I used. pastebin.com/z3hzcik4 \$\endgroup\$ – Ahmed Saleh Nov 19 '16 at 2:20
  • \$\begingroup\$ I tried to instantiate a ROM, and assign the address, but it shows black, does it means that the ROM has not initalized ?how would I verify that ? \$\endgroup\$ – Ahmed Saleh Nov 19 '16 at 2:22
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    \$\begingroup\$ signal addr: INTEGER RANGE 0 TO 15; so the memory only have 16 words. If you are not simulating already, you should. I probably will not proof-read code again, just not something I like to do. \$\endgroup\$ – rioraxe Nov 19 '16 at 4:04
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    \$\begingroup\$ Since you are addressing the ROM with an address of 16 words only (equivalent to 4 bits), all higher order address bits are ignored. The 16 words pattern is mapped to pixels repeatedly and that seems to match the repeated vertical bars on your video. \$\endgroup\$ – rioraxe Nov 20 '16 at 21:45
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    \$\begingroup\$ Debug with the simulator. Look at pixels with each hcounter and you should spot the repeating pattern. Add in submodule signals to the wave display (such as hcounter, vcounter and various address). Try to find why the repeating pattern. \$\endgroup\$ – rioraxe Nov 20 '16 at 21:57

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