How do I reset my registers on Digital Clock Manager output?

Question

I am using a SPARTAN 3E and have used the DCM core to generate a 50 Mhz to 25 Mhz clock to drive the VGA PORT. The reset logic I'm using is shown here.

DigitalClockManager instance_name (
.CLKIN_IN(CLK_50MHZ), 
.RST_IN(rst_in), 
.CLKFX_OUT(clk),         //25 Mhz
.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
.CLK0_OUT(), 
.LOCKED_OUT(LOCKED), 
.STATUS_OUT(STATUS)
);      
BUFG buffer (.I(CLKIN_IBUFG_OUT), .O(CLKIN)); 

RESET LOGIC :

    reg LOCKED_R;
reg [3 : 0] SR; 
always @ (posedge CLKIN)
begin
    if(RESET)
    begin
    SR [3 : 0]  <= 4'b111;
    LOCKED_R <=0;
    end

else 
begin
LOCKED_R <= LOCKED;
if(LOCKED < LOCKED_R | STATUS [1] ) // H to L on LOCKED | CLKIN UNSTABLE
SR <= {1'b1 , SR[3 : 1]};
else 
SR <= {1'b0 , SR[3 : 1]};
end
end

assign rst_in    = ( (SR[2] | SR[1] | SR[0]) || RESET);

Now, I am not sure about how to implement reset for all the other registers in the design.

    always @ (posedge clk) 
begin  
   if (LOCKED && !STATUS[1])
    begin 
           //GOOD TO GO
    end
    else

    begin
     //RESET
    end
end

If the RESET signal pulse lasts for a period shorter than what it takes to assert the locked signal, (which probably will be the case because of the OR gate at the rst_in), the registers will never be reset.

Does the always @ (posedge clk) trigger even when (LOCKED && !STATUS1) isn't high?If so, why doesn't the else part trigger and set registers to default values?

Answer 1

I think your logic is correct, except you mean to implement an asynchronous reset .i.e the reset is independent of the clock. This doesn't reflect in the code above and can be fixed by adding the LOCKED and STATUS signals in the sensitivity list of the process.

always @ (locked or status or posedge clk)