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I am using a SPARTAN 3E and have used the DCM core to generate a 50 Mhz to 25 Mhz clock to drive the VGA PORT. The reset logic I'm using is shown here.

DigitalClockManager instance_name (
.CLKIN_IN(CLK_50MHZ), 
.RST_IN(rst_in), 
.CLKFX_OUT(clk),         //25 Mhz
.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
.CLK0_OUT(), 
.LOCKED_OUT(LOCKED), 
.STATUS_OUT(STATUS)
);      
BUFG buffer (.I(CLKIN_IBUFG_OUT), .O(CLKIN)); 

RESET LOGIC :

    reg LOCKED_R;
reg [3 : 0] SR; 
always @ (posedge CLKIN)
begin
    if(RESET)
    begin
    SR [3 : 0]  <= 4'b111;
    LOCKED_R <=0;
    end

else 
begin
LOCKED_R <= LOCKED;
if(LOCKED < LOCKED_R | STATUS [1] ) // H to L on LOCKED | CLKIN UNSTABLE
SR <= {1'b1 , SR[3 : 1]};
else 
SR <= {1'b0 , SR[3 : 1]};
end
end

assign rst_in    = ( (SR[2] | SR[1] | SR[0]) || RESET);

Now, I am not sure about how to implement reset for all the other registers in the design.

    always @ (posedge clk) 
begin  
   if (LOCKED && !STATUS[1])
    begin 
           //GOOD TO GO
    end
    else

    begin
     //RESET
    end
end

If the RESET signal pulse lasts for a period shorter than what it takes to assert the locked signal, (which probably will be the case because of the OR gate at the rst_in), the registers will never be reset.

enter image description here

Does the always @ (posedge clk) trigger even when (LOCKED && !STATUS1) isn't high?If so, why doesn't the else part trigger and set registers to default values?

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I think your logic is correct, except you mean to implement an asynchronous reset .i.e the reset is independent of the clock. This doesn't reflect in the code above and can be fixed by adding the LOCKED and STATUS signals in the sensitivity list of the process.

always @ (locked or status or posedge clk)

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  • \$\begingroup\$ I really want to avoid an async reset.Is there no way around that? \$\endgroup\$ – Ahmed Ali Abbasi Nov 21 '16 at 6:06
  • \$\begingroup\$ The only potential issue I see with not having an asynchronous reset is that the quality of the clock when it's not locked is unknown. \$\endgroup\$ – dst Nov 22 '16 at 5:19
  • \$\begingroup\$ FDS flop00 (.D(1'b0), .C(clk), .Q(out1), .S(1'b0)); FD flop01 (.D(out1), .C(clk), .Q(out2)); FD flop10 (.D(out2), .C(clk), .Q(out3)); FD flop11 (.D(out3), .C(clk), .Q(out4)); What about this scheme for register reset? Default value at start up is 1 for FDS.As clock lock goes from high to low, I could set D input back to 1 which will then shift right, when clock becomes valid again, and I could just OR the FLIP FLOP outputs. One more thing, I am talking of resetting registers operating on DCM clock.Does the DCM reset seem logic right to you? Thank you! \$\endgroup\$ – Ahmed Ali Abbasi Nov 22 '16 at 13:35
  • \$\begingroup\$ what if the lock is lost after start-up ? As you have no control on the incoming clock signal. \$\endgroup\$ – dst Nov 28 '16 at 21:19
  • \$\begingroup\$ Yup! That is why one would link the first FF to the locked signal of the DCM. \$\endgroup\$ – Ahmed Ali Abbasi Dec 5 '16 at 13:28

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