S/PDIF to TTL converter

Question

This is how S/PDIF to TTL converter usually looks like. I simulated poor quality smoothed out signal with a sine wave.

Can comeone explain how it really works? Inverter with feedback resistor confuses me a bit. My intuitive approach would be to use a voltage divider to bias inverter's input to it's threshold point. On the schematic above it becomes properly biased automatically.

Answer 1

In the question's circuit

• A2 is used as an analog (negative) gain stage. Likely, the circuit is designed with A2 an un-buffered inverter, which can be linearized by negative feedback.
• A1 provides further gain, making the output digital. It also happens to restore the original polarity (within some phase shift), but that's immaterial given the bi-phase mark data modulation system of S/PDIF.
• R3 makes the impedance on the input close to 75 Ω.
• C1 allows the A2 stage to operate with a DC offset, and attenuates low frequency. Together with R1 (and A2), it forms a high-pass filter. That greatly improves the circuit's immunity to 50/60 Hz AC power ground loop currents. Loss of low frequency is fine given the bi-phase mark data modulation system of S/PDIF.
• R1 gives negative feedback to A2, stabilizing it's DC bias, and makes A2 operate in a linear region for small signal.
• R2 shifts A2's operating point, and likely stabilizes the output of A1 to high in the absence of signal (that would be the case if A1/A2 came from the same 74HCU04 circuit). Perhaps it lowers A1's gain, or makes it more reproducible. But I think removing R2 would not prevent operation, at least when there is signal.

Answer 2

R1 provides hysteresis to the comparator so that it will not "dither" when the voltage is close to the threshold.

https://en.wikipedia.org/wiki/Comparator#Hysteresis