I'm reading PCIe specification, which mentions that the communication between the root/end points are through switches instead of buses as for PCI, and this structure improves throughput as the traffic doesn't have to share media with others. However, many pictures of th structure of PCIe switches show that the ports (upstream/downstream) are internally connected using buses. So, is this structure still a switch?

  • \$\begingroup\$ You turn the PCIe serial transmissions into parallel busses to lower the internal frequency and allow multiplexing several flows. For example, a 4x 5GHz PCIe link will occupy half the bandwidth of an internal 625MHz 64bits bus. \$\endgroup\$
    – Grabul
    Nov 19, 2016 at 18:43
  • \$\begingroup\$ So they are actually buses, but as fast as, or even faster than line speed switches, right? \$\endgroup\$
    – fiedel
    Nov 19, 2016 at 18:55

1 Answer 1


All PCIe connections are point-to-point. A PCIe switch has more than two ports, so its internal connections could be described as a bus.

However, this is not necessarily how it's actually implemented. When the switch receives, for example, a packet on its upstream port, it puts it into a buffer, and uses the destination in the packet header to determine on which downstream port to re-transmit the packet. This implies that all ports can be somehow connected to the same buffer, but not that there is an actual bus on which the packet is transmitted and to which all output ports listen.

  • \$\begingroup\$ In nvme, the host(CPU) creates queues. So, when host writes to a submission queue(present in the host), will PCIe be responsible for taking that data and forwarding it to the queue of the nvme device? \$\endgroup\$
    – AlphaGoku
    Nov 11, 2019 at 10:04
  • \$\begingroup\$ @AkshayImmanuelD NVMe is just a protocol running on top of PCIe. \$\endgroup\$
    – CL.
    Nov 11, 2019 at 13:14
  • \$\begingroup\$ @AkshayImmanuelD No. The NVMe device is responsible for reading the data via DMA by issuing PCIe read requests. NVMe is just a specification for how the device operates over PCIe so NVMe devices from different manufacturers can all share the same NVMe device driver; I wouldn't even call it a "protocol." \$\endgroup\$ Jan 24, 2020 at 20:37

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