FPGA could connect to lot of devices like memory devices (SRAM, SDRAM, DDR RAMs), data converters and various other complex ICs. Is it a normal practice to model them in a testbench to make verification "complete"? I assume that doing so will atleast require a cycle accurate behavioural model.

Lets take example of SRAM or SDRAM, is it normal practice to use some sort of cycle accurate model of these memory devices in a testbench?

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    \$\begingroup\$ Yes. Some manufacturers even provide free simulation models (Verilog or VHDL...), for example Micron. \$\endgroup\$ – TEMLIB Nov 19 '16 at 22:05

If you are to use an external SRAM in your FPGA platform, then you need not only the "cycle accurate", but also (mostly) "timing-accurate" model, if you want something to work. The timing depends on particular memory chip and manufacturer, so the normal way is to download the model form manufacturer's site.

Again, you keep repeating your questions, but continuously mixing "SRAM" with "SDRAM" and other types of memory. The SDRAM (dynamic RAM) is totally different beast as compared to SRAM (static RAM), and requires much more complex on-FPGA controller, cycle-configurable and therefore very cycle-accurate. Same thing, the behavioral and interface timing model are coming from manufacturers.

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  • \$\begingroup\$ I understand the difference, I am in the "deep end" and trying to figure out as many things as possible. This is not the only thing I am doing. After reading the documentation from the Quartus Handbook on Qsys and documentation on Altera IP cores, I'm close understand how to use the msim_setup.tcl in my custom tesbench. I wanted to jump to DDR RAM but that is more complicated and will certainly need special timing constraints too. I know that SRAM and DRAM and SDRAM are different. I have read datasheets of each of them. The DRAM datasheet was quite old part though seems SDRAM is more popular. \$\endgroup\$ – quantum231 Nov 19 '16 at 22:16
  • \$\begingroup\$ I know that dynamic RAM needs refresh cycle and also needs to be recharged after we read data from it. However, SRAM is different and has simpler interface also. \$\endgroup\$ – quantum231 Nov 19 '16 at 22:17
  • \$\begingroup\$ I saw courses on Altera website also related to Qsys. When I posted question earlier I could not figure out why I am given option to create seperate testbench and simulation folders in the IP Catalog. When I executed the msim_setup.tcl, and invoked ld command, it started the simulation but there was no stimulus. It was not clear where my own testbench goes. Now I understand that I have to write a testbench and create a tcl script using "source msim_setup.tcl". \$\endgroup\$ – quantum231 Nov 19 '16 at 22:19
  • \$\begingroup\$ As it turns out, the reason for my confusion was a bug in the program. Qsys does not generate same files in the simulation folder when I select VHDL during generate HDL then when I select Verilog. I am using Quartus II 15.0 64 bit. As it turns out, a folder named submodules is not created in the simulation folder when I select VHDL in the simulation folder than when I select Verilog. The submodules folder contains a .v file containing source code of the memory controller. This submodule folder is created in the synthesis folder in both cases though. \$\endgroup\$ – quantum231 Nov 20 '16 at 12:21

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