I have to design a sequential circuit for a traffic light controller. It has 6 outputs, Red-Green-Yellow for North/South and East/West lights. What has to happen is that every 8 clock cycles (one clock cycle is represented by 1 button push, so after 8 button pushes, the lights switch) the lights have to change. So, the order would be

R(N/S)-R(E/W) -> R(N/S)-G(E/W) -> R(N/S)-Y(E/W) -> R(N/S)-R(E/W) ->
G(N/S)-R(E/W)-> Y(N/S)-R(E/W) -> R(N/S)-R(E/W) -> R(N/S)-G(E/W)... and so on.

I have created a diagram, truth table, and equations. As far as I can tell, I have everything connected and put in correctly (We're using quartus to program a DE0). I have a 3 bit register connected to the combinational circuit for my state machine.

Only thing I can think of being wrong at this is that my initial design is completely wrong. What's happening is that after 8 clock cycles the state doesnt change.

Here are pictures of my state diagram, truth table, k-maps, and equations. Ignore the min terms box. Its just a way I sort through the truth table because it is hard to read.

EDIT: What I am asking is, is my design sound? Am I fundamentally making a problem with the state diagram?

enter image description here

enter image description here

  • \$\begingroup\$ Homework question, but with attempts to solve and clear explanations of what you tried and what's happening. Wow. Have my upvote. \$\endgroup\$ – dim lost faith in SE Nov 20 '16 at 20:32
  • \$\begingroup\$ I don't understand completely but checked N2. It makes sense. What I don't understand if how T is generated and what the push button is doing. Do you have a separate counter circuit that is just outputting T every eight clocks. If that is what is going on, is it the same clock that is clocking the p0-2 register? If you have the right inputs at the register did you make sure the register is not being held reset? \$\endgroup\$ – owg60 Nov 20 '16 at 20:53
  • \$\begingroup\$ I have a seperate module, that acts as the clock. Every 8 cycles it outputs T. Here is an album of my design imgur.com/gallery/sleXL \$\endgroup\$ – Melendowski Nov 20 '16 at 20:55
  • \$\begingroup\$ I have a seperate module, that acts as the clock. Every 8 cycles it outputs T. The clock takes an 2 inputs Button[1], which resets, and Button[2] which is the clock. At 7 pushes of Button[2], T should output and LEDG[9] should turn on. It does. On the 8th push of Button[2] the states should change. They dont. Here is an album of my design imgur.com/gallery/sleXL \$\endgroup\$ – Melendowski Nov 20 '16 at 21:01
  • 1
    \$\begingroup\$ I'm ignorant of the DE0 so this may not be helpful. What I see on the top level is RESET coming out of an inverter. I read this as the system is reset when RESET is high and that it is low most of the time. I'm confused by the off pages all saying Vcc on them. Do the signals just pass to the next level even though the offpages say Vcc? On the three bit register I see RESET connected to the clear bubble of the D flip-flops. How do I read this correctly? It looks to me like the D flip-flops can't change because RESET is holding it. \$\endgroup\$ – owg60 Nov 20 '16 at 21:28

This isn't a direct answer to the question, but something you need to know that you haven't even realized is a issue yet.

You want something to happen where individual button pushes are individual events. However, real mechanical buttons don't work that way. They "bounce". What is a single button push to you, can actually be 10s of individual connections and disconnections until the button finally comes to rest and stays steady in the new state. If you just hook up a button with a pullup resistor to a digital logic input, each button press will actually be interpreted as many. The digital logic is fast enough to process individual bounces.

To fix this, you do something called debouncing. There are a number of ways, but with that search term you should be able to find plenty on the subject.

The simplest way is to not consider the new state valid until it has been steady for the debounce interval. This needs to be long enough to wait for the switch to stop bouncing. That's usually 10-20 ms. However, I like to use 50 ms debounce time. That's about the longest that humans won't notice. Some switches do bounce nearly that, so you might as well since it's free in terms of human perception.

|improve this answer|||||
  • \$\begingroup\$ Yeah that's probably it. His outputs are not changing at all because his switch closures are bouncing. I can't up vote an answer like this. I wonder who could. \$\endgroup\$ – owg60 Nov 21 '16 at 10:42
  • \$\begingroup\$ No, its not this. \$\endgroup\$ – Melendowski Nov 27 '16 at 22:37

I am not sure if I should answer my own question, but I figured it out.

The reset for the flips of the State Machine register required a NOT gate. This is because everything is backwards with the FPGA I am using (DE0).

|improve this answer|||||
  • \$\begingroup\$ You don't require a NOT gate. Considering your new question you don't seem to understand normally high and normally low switches and how to assign them correctly. I suggest you look up what the terms "active high" and "active low" mean, the FPGA on the DE0 board is a Cyclone III EP3C16F484 by the way, DE0 is the development board, not the FPGA. \$\endgroup\$ – Doodle Dec 21 '16 at 10:26

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.