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I've been building a project using some Infineon IPA093N06N3 MOSFETs. I carefully picked the correct values for the MOSFET that I needed, and calculated an estimated Tj based on the thermal resistance of the package I was using.

I only just noticed today the Safe Operating Area graph in the datasheet whilst looking up the pinout for the package. The SOA suggests that this MOSFET (and a lot of others I took a look at afterward) is only rated to "safely operate" in a very small window, despite the much larger maximum operating conditions listed on the first few pages of the datasheet.

Taking the linked datasheet above as an example, it states that the MOSFET is capable of a VDS of 60V and a ID of 43A. A further look on page 4 shows the SOA graph, which states that at any VDS over 10V you are limited to a ID of 10A. I previously assumed that, so long as you stayed inside the maximum ratings and you could cool the MOSFET to below Tj(max), that any value for both of these would be alright.

If the MOSFET is capable of switching a large current whilst staying under the Tj(max), what other limiting factors might there be that would cause the manufacturer to state that they are only capable of smaller currents above certain voltages?

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    \$\begingroup\$ With a Vds of 10V the FET is not fully on. If you are using PWM for example, you will only be during that state for a brief period of time. \$\endgroup\$
    – Wesley Lee
    Nov 21, 2016 at 6:16
  • \$\begingroup\$ @WesleyLee I thought that the Vgs determined the FETs state, not the Vds? (I understand that the on-state is also determined by Vds > Vgs - Vth, but in my situation, this holds true.) \$\endgroup\$
    – jduncanator
    Nov 21, 2016 at 6:17
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    \$\begingroup\$ I made a very similar question to yours a few months ago, see if it helps you: electronics.stackexchange.com/questions/153588/… \$\endgroup\$
    – Wesley Lee
    Nov 21, 2016 at 6:18
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    \$\begingroup\$ The voltage across the FET is different than the voltage across the FET + the load. Max Vds has to be the voltage across the FET + the load, Vds on the SOA is the voltage across the FET exclusively, which happens during a brief period of time when swicthing on/off. \$\endgroup\$
    – Wesley Lee
    Nov 21, 2016 at 6:28
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    \$\begingroup\$ It does apply when using a FET as a switch, during the period that the FET is not fully on or off. The more time you spend switching on/off, the more time you spend with a High Rds, thats one of the reasons why you want a driver that can turn the FETs gate on/off fast. \$\endgroup\$
    – Wesley Lee
    Nov 21, 2016 at 6:33

1 Answer 1

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With a Vds of 10V you should be in the linear are of operation of the FET (not fully on).

In a switching application, that is a "switching" loss. When fully on, you will approach the lowest Rdson that your given Vgs can achieve, and that would be a "conduction" loss.

enter image description here

Image source

The voltages on the SOA graph are not the voltages across the FET + the load, just the voltage across the FET.

schematic

simulate this circuit – Schematic created using CircuitLab

If the FET is "off", then the drain will "float" up with the load (so Vds will be high, but current will be very low). When its "on" Vds will be very, very low (Rds * current), and current high. So provided your FET is properly turned on, it should spend very little time on the upper-right part of the graph.

enter image description here

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  • \$\begingroup\$ Not sure where you copied the diagrams from but the RHS Load FET diagrams is incorrect. It shows VDS at -0.1 V with a 10 Ohm resistive load and 60 V supply. This won't ever occur. \$\endgroup\$
    – Jack Creasey
    Nov 21, 2016 at 17:14
  • \$\begingroup\$ @JackCreasey I believe that is a tilde (~) not a negative (-) but I could be wrong. \$\endgroup\$
    – jduncanator
    Nov 21, 2016 at 22:58
  • \$\begingroup\$ @JackCreasey -- thanks for pointing that out. It was indeed a ~ to point out an approximation, I substituted it. The diagram is there to provide some illustration on Rds / Vds during the linear region, which might be confusing if you interpret the FET as a "switch". \$\endgroup\$
    – Wesley Lee
    Nov 23, 2016 at 11:14
  • \$\begingroup\$ +1 Nice answer. I was wondering.. where's the first picture taken from? \$\endgroup\$
    – m.Alin
    Nov 23, 2016 at 11:49
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    \$\begingroup\$ @m.Alin -- maximintegrated.com/en/app-notes/index.mvp/id/4266 \$\endgroup\$
    – Wesley Lee
    Nov 23, 2016 at 13:27

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