I'm putting together a small PCB based around a Xilinx Zynq (the CLG225 one), because the DDR3 pads are all in a big block on one side of the device and because I've been designing for a 4 layer PCB, the traces have had to be routed with ~80ohm single ended impedances.
My question is this: With a single 16bit DDR3 chip ticking over at 400MHz (800Mbps), am I going to run into unacceptable signal integrity issues if all the traces are 80 ohms but are kept under 20mm? Or, are 20mm traces short enough to avoid any serious transmission line effects with DDR3-800 memory?
Most recomendations advise 40 ohm traces, but there just isn't enough room for tracks that wide (and no, I can't change the stackup, it's with OSH park and it's just for fun) All byte groups are length matched to <0.5mm of course and so are all the command and address lines, it's just that the impedance is twice the recommended value. There are unbroken planes beneath all signal lines.
This is not for a product, this is not really even a proof of concept, if I was to go to 8 layers, it'd be a cinch, but I just want to see if it can be done with a hobbyist only fab and I'd like to hear from someone more experienced in the field than me if it's even going to work in the first place.