# VHDL: Using type on ports

Is it poosible to use user-defined typed in input/output of VHDL enitities?

ENTITY test IS
PORT(
input         : IN     std_logic_vector (0 TO 63);
test_input:   out MY_TYPE;
);

END test ;


Yes, declare the type in a package, and use the package before the entity, and also in the modules that instantiates the module, so the same user defined type is available.

• can you bring a sample code please? – VSB Nov 22 '16 at 9:34
• – Morten Zilmer Nov 22 '16 at 10:38