Is it poosible to use user-defined typed in input/output of VHDL enitities?
ENTITY test IS
PORT(
input : IN std_logic_vector (0 TO 63);
test_input: out MY_TYPE;
);
END test ;
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Sign up to join this communityIs it poosible to use user-defined typed in input/output of VHDL enitities?
ENTITY test IS
PORT(
input : IN std_logic_vector (0 TO 63);
test_input: out MY_TYPE;
);
END test ;
Yes, declare the type in a package, and use the package before the entity, and also in the modules that instantiates the module, so the same user defined type is available.