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I have the following circuit: Driver

The circuit is working fine, but the problem is that when there is no load, the IRF9540 are getting hot. When they are in load, they are cold. For sure, I think it's a problem with the gate-source resistors.

I measured the voltage drop between G-S on the IRF9540 and I have the following values: -3.5V in no load and ~-11V in load.

I don't know how to tune the circit to remove this no-load heating, so I'm asking for your help. Thank you !

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    \$\begingroup\$ What exactly do you mean when you say 'no load'? \$\endgroup\$ Nov 22, 2016 at 15:29
  • \$\begingroup\$ Both switches are open (I forgot to open the left one in the picture). \$\endgroup\$
    – user126120
    Nov 22, 2016 at 15:32
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    \$\begingroup\$ Well then, none of your mosfets gates are being pulled all the way one direction or the other when you have the switches open. try removing r3 and r4, they are simply creating a voltage divider which can turn all of your mosfets on. \$\endgroup\$ Nov 22, 2016 at 15:39
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    \$\begingroup\$ Then you're fine. 20 Volts is the max. I'm willing to bet that is your issue. When your BJTs are off, the gates of the MOSFETs are held at 6 volts, and they have a threshold voltage of 4V (maximum). i.e. neither are turned fully off. \$\endgroup\$ Nov 22, 2016 at 15:51
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    \$\begingroup\$ Take those 2 resistors you removed and put them across the base-emitter of your NPN transistors. Make sure that they really are off when the switches are open. And your measurements don't add up: Vgs-Ntype + Vgs-Ptype should equal your supply voltage if you've got them connected as per your diagram. \$\endgroup\$
    – brhans
    Nov 22, 2016 at 16:17

1 Answer 1

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The trouble lies in the design of the gate driver. When transistor Q5 is off, resistors R1 and R3 form a voltage divider that sets the gates of Q1 and Q3 at half the supply voltage, nominally 6V. This is enough to turn on both FETs at the same time, causing a current to flow through them. Since you are measuring only -3.5V instead of -6V, it appears that the current is large enough to cause the supply voltage to sag. The reason the P-channels are getting hot is they have lower trans-conductance than the N-channels, and are seeing the majority of the voltage drop.

You need to re-design the gate driver so that only one of the FETs in each half-bridge can be on at a time. The other FET must have its Vgs close to zero volts.

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