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To works well, inside a multiplexer we need the input signals inverted, but can we use a pmos instaed of a nmos with a inverted signal to delete the inverter? Is there any thouble? PSpice give me some problem.

For example i try on PSPice a multiplexer 2 -> 1

enter image description here

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  • \$\begingroup\$ What you describe sounds like two N-mos fets parallel. What was the reason that a P-fet was present in the first place? \$\endgroup\$ – Wouter van Ooijen Nov 22 '16 at 16:51
  • \$\begingroup\$ As he stated, to prevent needing the inverter to generate opposite polarity select signal. \$\endgroup\$ – jbord39 Nov 22 '16 at 16:54
  • \$\begingroup\$ That doesn't answer my (rethorical) question. Why was the P-mos present in the original design? (jbord39 answered this). \$\endgroup\$ – Wouter van Ooijen Nov 22 '16 at 17:54
  • \$\begingroup\$ The original design has only Nmos that uses signal and inverted signal. Like this -> 4.bp.blogspot.com/-sHAShLxGZsU/VtGgzeVm4hI/AAAAAAAAADo/… \$\endgroup\$ – Alan Nov 22 '16 at 18:29
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Yes you can do this but a PMOS can only pass a solid '1' while an NMOS can only pass a solid '0'. Otherwise there is one threshold voltage drop across the pass gate.

This makes it hard to chain longer structures together because you lose voltage at each stage and so you must rebuffer the signals (inverter or something to restore logic levels).

The solution to this is to use a transmission gate which is parallel NMOS/PMOS with opposite polarity gate signal as the select.

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  • \$\begingroup\$ Thank you for your help! My teacher ask me to find why in classroom we don't use both to eliminate inverted signal. He doesn't talk about Cmos pass transistor. How do you think can i formally reply him? \$\endgroup\$ – Alan Nov 22 '16 at 18:30

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