# What is the standard way to represent fixed point numbers in VHDL?

Is there a native type in VHDL language similar to std_logic_vector that allows one to create a signed or unsigned fixed point number for given length of fractional and whole parts? If so, can it be synthesized?

How does one see fixed point quantities in wave window in test bench? Does one need to create a variable of type real and then use it to represent the fixed point quantity after manual conversion?

Are there functions in VHDL 2008 for conversion to and from fixed point and VHDL real type?

• There is no standard fixed point libraries (or representations) in VHDL. Commented Nov 23, 2016 at 14:42

If You'd like to implement fixed point arithmetics in synthesizable VHDL you have two ways:

1. Do It Yourself. It's rather hard method, but it may depend on quantity and complexity of equations You want to implement. Generally every "variable" should have two parts (integral and fractional) made of std_logic_vectors. Of course You have to implement basic (addition, subtraction etc.) mathematical operations.
2. Just download and use package fixed_pkg, it implements signed and unsigned fixed point types and all basic math - more here.

But first of all - do You really need fixed (or floating) point types? Most math could be done on std_logic_vector, just like we do in microcontrollers using int types.

EDIT:

Unfortunately, link to the libraries inside pdf guide from above link is dead. Someone delete the files. But it shouldn't be a problem - currently all ieee_proposed libraries are moved to standard VHDL2008, so just change the used standard in the properties of Your project.

• Sadly if you follow the trail in the "more here" link, it leads to a dead end. Commented Nov 23, 2016 at 16:05
• I have to draw mandelbrot set, and thus need them. What is difference between fixed_pkg and fixed_generic_pkg? Commented Nov 23, 2016 at 16:06
• Why not just use std_logic_vector and make sure that it is shifted correctly before and after all arithmetic operations? I am surprised by your description of having to create two parts for every number. Commented Nov 23, 2016 at 16:11
• @quantum231 If You use one std_logic_vector for every number (and just remember where is the "point") it will be exactly the same like using ordinary int in C. Commented Nov 23, 2016 at 16:24
• @vicatcu What's the matter? There is a 15-page PDF in the link? Commented Nov 23, 2016 at 16:25

What is the standard way to represent fixed point numbers in VHDL?

There is none.

"Fixed point" is an interpretation of a number. The waveform display interprets the binary vector in a certain way. I don't know whether you can change that interpretation (in Xilinx Vivado, you can, to an extend, with a click of your right mouse button...), but it's basically not worth much: For all means and purposes, you use fixed point numbers to be able to treat fractional quantities like integers.

• Doesn't use of sfixed and ufixed amount to a standard method? After all this is what they were created for right? Commented Nov 23, 2016 at 16:13
• no. The whole point in using HDLs is that you get the freedom to choose whatever format fits your application. Thus, anyone telling you "this is a standard format" hasn't understood that you parameterize your HDL design for your algorithm, not the other way around. Commented Nov 23, 2016 at 16:16
• I think the words 'standard method' were meant as 'typical method' and not to mean 'defined by a standard' :-) You do get freedom to choose but people tend towards a few oft-used and familiar methods. Commented Nov 23, 2016 at 22:21
• @MarcusMuller, I can see the point you're making though, being VHDL, I imagine you mean designer, not programmer :-) But the opposite extreme is custom formats and functions that save less then they cost in the learning curve of other engineers for code reviews, testing and for reuse in other designs. It's somewhere between those and choosing recognisable formats is a virtue when assessed against all things. I do sympathise with your attitude to waste and bad design. Commented Nov 24, 2016 at 9:06
• "Fixed point" is a mapping of a mathematical concept to its representation in logic signals. I cannot see why referencing the same VHDL-type would be a drawback for designs using the same mapping. It makes IP interoperable. You are still free to define whatever you want, if you are better off with a non-standard representation like sign/magnitude. What's your point? Commented Nov 24, 2016 at 20:26