So i am going through this excellent book Patterns for Time-Triggered Embedded Systems and have a question regarding calculating values for hardware timers precisely. See "Hardware Delay" pattern in the above book.
My understanding is that, a "clock source" (aka "System Clock") generates a steady series of ticks (say f1 khz) which is then fed through a "Prescaler" unit which divides it (by a factor n which can be 1) giving another frequency (say f2=f1/n khz) which is then fed to the processor. Thus the "Processor Clock" has a frequency f2 and time period t2=1/f2 ms. To calculate a precise time interval (eg. 100ms timer) we just calculate the number of ticks in 100ms like 100/t2 = f3 "processor clock ticks". So we need to setup the appropriate timer registers to values corresponding to f3 to generate a 100ms tick.
However it does not seem to be so straight-forward (at least for the 8051) because of the number of ticks required for a "processor instruction cycle". A processor goes through its instruction cycle i.e. "Fetch->Decode->Execute->Interrupt" (interrupts are checked at the end of the current instruction) which takes a series of ticks. Ideally the entire instruction cycle should take just 1 tick (eg. a pipelined processor) and so i can use the above calculation to setup timers. However, apparently in the original 8051, the System clock ran at 12 mhz and each instruction cycle took 12 ticks. Since interrupts are checked only at the end of the instruction cycle, we now need a further division by 12 to get the correct "timer" clock tick, which is "processor clock"/12 i.e. f2/12.
Is my above understanding correct? If true, how can i calculate precise timings when instructions can have different cycle ticks (eg. mixed 32 and 16-bit instructions). Also do timers have to be incremented via a processor instruction cycle or is there a way in HW to increment a timer register strictly in sync with the output of the "Prescaler" unit?