I have a question about the instantiation. Like the picture shown below, if my main code is 3.vhd. I want to instantiate entity aaa and bbb in entity MAIN. Is the rule that I should write the "component" in "package", like 1.vhd shows? (My understanding is, all the entity should have its package, if it'll be instantiated. And the component just list the port of this entity.) After that, add "use package.all", and then we can instantiate aaa and bbb in MAIN's architecture. Is there anything wrong?
I'm not familiar with VHDL, but seems verilog didn't have this "package" thing. A module can be instantiated in another modules.