I have a question about the instantiation. Like the picture shown below, if my main code is 3.vhd. I want to instantiate entity aaa and bbb in entity MAIN. Is the rule that I should write the "component" in "package", like 1.vhd shows? (My understanding is, all the entity should have its package, if it'll be instantiated. And the component just list the port of this entity.) After that, add "use package.all", and then we can instantiate aaa and bbb in MAIN's architecture. Is there anything wrong?

I'm not familiar with VHDL, but seems verilog didn't have this "package" thing. A module can be instantiated in another modules.

Thanks! :)

enter image description here


For simple setups, you can get away with directly instantiating entities:

entity aaa is
    port( ... );
end entity;

architecture foo of aaa is
end architecture;

And then in the other source file:

architecture foo of main is
    AAA : entity work.aaa
        port map( ... );
end architecture;

That is the quickest way to not repeat yourself too much.

Separate component declarations inside a package become useful if you have exchangeable parts and multiple different configurations that combine them in different ways. Unless you need that, go with direct entity instantiation.

  • \$\begingroup\$ Thanks! That looks like verilog module instantiation now..... :) \$\endgroup\$ – Nobody Nov 24 '16 at 13:47

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