For the diagram below, I can see that it functions as a monostable (I have built and tested it), but I can't really see why it works, I mean, I can see that there is an RC network, which a monostable has, but I don't see how it links up with the logic to make a monostable.

Any help would be appreciated

The diagram in question


1 Answer 1


A better drawing of the same circuit can be found here.

enter image description here

Where there is also an explanation.

In your circuit one of the inputs of U2 is connected to Vcc but that makes no difference to the behavior of the NAND gate. Make the truth table for a NAND and you'll notice that in both cases U2 acts as an inverter.

When the button is pressed, the output of U1 will become high, it was low so Ct was not charged (it discharged via Rt). Since Ct is not charged V1 will also be pulled high and a current though Rt starts to charge Ct.

As V1 becomes high, U2's output becomes low (U2 behaves as an inverter). This low signal gets back to U1 and keeps the output of U1 high. So Ct can charge. As it charges the voltage V1 drops untill U2 flips over and it's output becomes high. If you have released the button as well, this will cause the output of U1 te become low again as it was before the button was pressed.

  • 5
    \$\begingroup\$ Caution: This circuit straddles between "logic" and "analog" domains. Logic family matters. You get different results using NAND gates from different logic families (7400, 74LS00, 74HC00, 74HC132, CD4093 etc.). Any equations that relate RT*CT time constants to pulse-width are specific to one particular logic family. \$\endgroup\$
    – glen_geek
    Commented Nov 24, 2016 at 16:16
  • \$\begingroup\$ This version with both inputs of U2 connected to Ct is better because the falling edge of U1 will stress the input protection diodes inside U2. If the current is shared between two inputs, they will survive longer. \$\endgroup\$
    – Jens
    Commented Jun 22, 2022 at 20:43
  • \$\begingroup\$ Rt must be small enough to pull down the input to U2 to logic 0, in the absence of a pulse. \$\endgroup\$
    – Bill
    Commented Jun 5, 2023 at 12:28

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