0
\$\begingroup\$

For the CMOS inverter the text states "once the transients have settled, a path always exists between VDD and the output realizing a high output (“one”), or, alternatively, between VSS and output for a low output (“zero”). This is equivalent to stating that the output node is always a low-impedance node in steady state."

What does the last statement about low impedance mean?

\$\endgroup\$
  • \$\begingroup\$ ... It means that the output is close to one of the rails provided a comparatively large load impedance is present. \$\endgroup\$ – Ignacio Vazquez-Abrams Nov 25 '16 at 0:53
  • \$\begingroup\$ This is in contrast to TTL or RTL or OC logic where the impedance is higher and unsymetrical. \$\endgroup\$ – KalleMP Nov 25 '16 at 6:54
2
\$\begingroup\$

Mosfets can be used as switches. In a cmos buffer one of the switches is to Vdd and the other is to Vss. A switch has two states; open or high impedance; or closed or low impedance. So when output of the cmos buffer is high, the switch to Vdd is closed. We can tell that this is low impedance by adding a load and seeing the effect. At no load the output will be Vdd. If we add load up to the Ioh specification, the output will stay close to Vdd indicating a low impedance path to Vdd. Similar for low to Vss.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.