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I have designed a simple PLL with current-starved ring VCO. The minimum frequency of oscillation for this VCO is zero since there is no current fed to ring of inverters when control voltage is zero.

As described in Chapter on Digital Phase Locked Loops in Jacob Baker's CMOS Circuit Design, Layout, and Simulation (Second Edition, Page 554)

"The frequency of the square wave output of the VCO is Fcenter when Vin(= Vcenter) is VDD/2 (typically). It is important that the VCO continues to oscillate with no input data."

Why is it essential for VCO to continue oscillating when input is zero? It would not be so if a current-starved VCO is used.

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  • \$\begingroup\$ Well, we'll need more context from the book to answer that… for what purpose is the VCO used in the book? and: can the VCO start itself without interaction, just by having a voltage applied, and how long does it take to stabilize? \$\endgroup\$ Nov 25, 2016 at 13:03
  • \$\begingroup\$ The VCO is used in a basic second order PLL. \$\endgroup\$
    – JGalt
    Nov 25, 2016 at 13:15
  • \$\begingroup\$ also, R. Jacob Baker has about three books in different editions that might contain a paragraph about VCO's – so a proper citation with title of book, page and edition would certainly help \$\endgroup\$ Nov 25, 2016 at 13:15
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    \$\begingroup\$ it's not essential, without other context at least. I've made PLLs where the VCO is allowed to stop at the bottom end of its tuning range. Now if I made part of the locking mechanism clocked from the VCO, then a stopped VCO would disable the tuning, and the system would hang. But that's a rather contrived example that nobody in their right mind would design, at least not design a second time! \$\endgroup\$
    – Neil_UK
    Nov 25, 2016 at 14:05

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Why is it essential for VCO to continue oscillating when input is zero?

I disagree with the statement that it is essential to keep the VCO oscillating for any input signal.

You could look at that statement in a broader sense: Is it needed to have the VCO oscillating for all possible input signals ?

A PLL is a feedback loop in which part of the signal is a frequency. What happens if that frequency becomes zero, i.e. DC ?

In my opinion this depends on the implementation of the frequency detector in the PLL. As long as that frequency detector considers DC to be a lower frequency than the reference frequency and therefore tries to set the chargepump such that the VCO will be steered to a higher frequency. Then the loop will eventually lock.

More dangerous is if the VCO stops because of a too high input signal (tuning voltage) because then the sign of the loop suddenly reverses (a slightly higher tuning voltage makes the VCO frequency go to DC). This will lock-up the loop as negative feedback (good) has changed to positive feedback (unwanted).

Note that this also might happen if the VCO produces such a high frequency that the frequency divider stops working !

To make the PLL lock quickly it is indeed more desirable to have the VCO oscillating for the full input signal range as it takes more time to start up a VCO than it takes to change its frequency. So desirable but not essential ! And depending on the phase-frequency detector of course.

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"The frequency of the square wave output of the VCO is \$f_{center}\$ when \$V_{in}(= V_{center})\$ is VDD/2 (typically). It is important that the VCO continues to oscillate with no input data."

It is important because if the VCO oscillate at the center frequency the time to lock when data arrive (i.e. to reach the new frequency) is minimum.

P.S. The book is CMOS Circuit Design Layout and Simulation

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  • \$\begingroup\$ But it would not be so if a current-starved ring VCO is used in the loop (which the author uses in subsequent sections) \$\endgroup\$
    – JGalt
    Nov 25, 2016 at 13:20
  • \$\begingroup\$ Why wouldn't it be like that? A PLL is a control loop. you don't want any of the systems involved to exhibit a step response! \$\endgroup\$ Nov 25, 2016 at 13:20
  • \$\begingroup\$ And I must admit that I'm not an expert on CMOS current-starved ring circuits, but as far as I can quickly grok their function, they, too, need at least one "ring" worth of oscillations to become stable, and I especially don't see why bringing the CMOS array into a different thermal point will make the gate charges at the FETs especially reproducible. \$\endgroup\$ Nov 25, 2016 at 13:23
  • \$\begingroup\$ If you can quickly check the part on current starved VCOs, you would see that the control voltage determines the current that is fed to the ring of inverters. If the control voltage is zero (when input to PLL is zero), current will also be zero. The VCO wouldn't oscillate at all. \$\endgroup\$
    – JGalt
    Nov 25, 2016 at 13:33
  • \$\begingroup\$ If not oscillating, there are no edges, and there is no phase information, thus no corrective voltage. \$\endgroup\$ Feb 13, 2017 at 3:32

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