# Logic function of cmos circuit with feedback

What is the best way to find the logic equation for f1 and f2 in the static CMOS circuit below. This circuit has partial pull up network made up of just one PMOS and full pull down network with NMOS transistors for each of boolean inputs

My solution to this yields that f1= ~a.~b ; f2 = a+b. But it is incorrect.

UPDATE: My explanation to my solution(possibly incorrect)

Observation

1. f1 = 0 when either a =1, b=0 or a=0,b=1 or a=1,b=1
2. f2 = 0 when a=0, b=0
3. f1 = 1 when f2 = 0 (in step 2)
4. f2 = 1 when f1 = 0 (in step 1)
5. No combination of a,b will make f1=1,f2=1 or f1=0, f2=0 simulataneously

Therefore we can conclude that f1 and f2 are always complement of each other.

From step 3, f1=1 when f2 = 0 which in turn happens when a=0, b=0. Drawing truth table for f1

a b f1
0 0 1
0 1 0
1 0 0
1 1 0


This means

f1 = ~a.~b


Similarly, from step 4, f2 = 1 when f1=0 which in turn happens when either a =1, b=0 or a=0,b=1 or a=1,b=1. Making the truth table for f2

a b f2
0 0 0
0 1 1
1 0 1
1 1 1


Therefore,

f2 = a+b

• You missed the flipflop logic in your equations. – Janka Nov 26 '16 at 9:56
• Also, the bottom logic blocks, the left is an AND and the right side is an OR. – tcrosley Nov 26 '16 at 10:20
• @tcrosley You're right, the circuit structure (series = AND, parallel = OR) is OR and AND but the AND is fed with the not(a) and not(b) while the OR is fed with a and B. – Bimpelrekkie Nov 26 '16 at 12:12

Simply determine when f1 is pulled to ground:

this is when not(a) and not(b) are both high.

So:

f1 = 1 when a = 0 AND b = 0


Now when is f2 pulled to ground:

f2 is zero when a = 1 OR b = 1


So truth table:

a  b   f1  f2
0  0   1   0
0  1   0   1
1  0   0   1
1  1   0   1


So:

f1 = not( a OR b)


and

f2 = (a or b)


You can effectively ignore the two PMOS at the top, this circuit only allows f1 = f2 = 1 (all NMOS would be off but this cannot happen in this circuit) or f1 = not(f2) so basically an inversion.