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So i have this shift register

enter image description here

With the initial values of ABCD (1101)

And the question is, how will this change after 4 clock pulses.

As I understand it, this shift register goes shifting the values from left to right. My first guess was basically taking the the lsb and putting it in first place and repeating the procedure 4 times (4 clock pulses).

I would then get ABCD (1101)

This is not the correct answer though.

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    \$\begingroup\$ Why guess, when the diagram shows you what's there? Why shift the output into the input, when the diagram shows you there's a gate combining the A and D outputs before they go back in? \$\endgroup\$
    – Neil_UK
    Nov 26 '16 at 14:53
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For the correct answer consider the value shifted into the left most bit position to be the Exclusive OR of the current states of A and D. So, for the first shift since A and D are both 1's the Exclusive OR would be zero and zero would be shifted into the left most bit.

(A list of logic symbols which includes what "=1" means can be found here.)

That is to say, starting with A, B, C & D being 1101, the next state would be 0110. And the state after that would be 0011. Armed with this information it should be easy find the 3rd and 4th states.

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  • \$\begingroup\$ You are one great asset to mankind. Such good explanation. Can't thank you enough. For anyone wondering, my answer finally became ABCD (0100). Thank you! \$\endgroup\$ Nov 26 '16 at 15:07
  • \$\begingroup\$ @st2000 what "=1" means is key, I've never seen xor depicted in that way before, nice wikipedia reference! \$\endgroup\$
    – vicatcu
    Nov 26 '16 at 18:48

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