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In a design I'm working on I've got a few discrete sections with dedicated purposes, mostly independent of each other but with a few basic interconnects (e.g. SPI / UART).

In order to make testing during fabrication easy I've isolated the power and ground nets for each section with 0R resistors, so that I can easily power up and test each section at a time. Each section also has its own decoupling capacitors with a single connection to ground and power rails at the 0R resistors.

As an example, I've got an Atmel ATMega328P-AU with its own +5V and GND nets, which then has a 0.1uF ceramic for decoupling, before passing through a pair of 0R resistors to the main ground and power planes. I've then got an LED display driver (MAX7219) with the same design, but with 1uF and 10uF reservoir capacitors due to the higher current demands, again with 0R resistors connecting the nets to power and ground. I'm doing the same again for an ESP8266 module.

My design isn't particularly sensitive and isn't going in an environment where people care about RF noise (aside from legal requirements), but I'm trying to be as careful as possible because any maintenance work on them is going to be near impossible after deployment, and I don't want them glitching out. The supply itself is expected to be fairly clean and I'm driving everything off a DI ATP1509-50 buck regulator.

Is this a sensible approach? Are there any guidelines for good practice on when/how to split power and ground nets like this?

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  • \$\begingroup\$ I do not split ground planes without a very good reason - it generally causes more harm than good. I would be comfortable with 0R resistors in the power nets. \$\endgroup\$ – Matthew Nov 27 '16 at 22:45
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It depends where you place 0R resistors.

Something that can be done is at the ouput of a regulator (DC/DC, LDO, etc.) with a correctly sized resistor regarding the current. For instance don't use a 0402 resistor for a 3A load.

A quick remark on 0R resistors: they sould have a maximum resistance specified b the manufacturer, for instance Rmax = 20mOhms. So you should the dissipation accordingly. For instance 20mOhms with 3A current lead to a 60mV voltage drop and 180mW dissipated power so a 125mW-rated 0805 package won't fit.

I've seen this implementation on a complex board featuring a high-end FPGA and a lot of memory chips. Each voltage was done by a specific regulator and a low value resistor (0.005 or 0) was put at the ouput. These resistors were not mounted during the assembly and we would solder them after checking each power supply group. The low value resistor allowed us to probe the current flowing just with an easy voltage measurement.

Separating the same voltage loads by multiple 0R resistors is a bad move. With the kind of board you're working, it should be fine. But you'll take a bad habit and if you work on complex boards with low voltages and high currents (processor or FPGA), you'll face power integrity issues.

With complex board you'll have a 4, 6, 8 layers board or even more. That means dedicated power planes layers. But to reach internal power planes from your regulator you'll use via. The more current you have the more via you'll place, but if you separate each load with a 0R then you have to go from internal layer to external layer to reach you resistor through via and then again to go again into internal layers. And if you're not careful enough you can easily forget the necessary number of via required by current.

In your case you only have one regulator per voltage and not one per load. So I won't recommend splitting your power planes.
Power down or power enable features exist and should be used if present. If you have a clocked component, removing the clock will make it act as in power-down.
Finally if you really want to measure the power of the feature, do a measurement with the function, unsolder all components of the function and do a second measurement.

Finally, never ever split your ground with 0R resistors unless you really know what you are doing (and this is not the case)

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