In a design I'm working on I've got a few discrete sections with dedicated purposes, mostly independent of each other but with a few basic interconnects (e.g. SPI / UART).
In order to make testing during fabrication easy I've isolated the power and ground nets for each section with 0R resistors, so that I can easily power up and test each section at a time. Each section also has its own decoupling capacitors with a single connection to ground and power rails at the 0R resistors.
As an example, I've got an Atmel ATMega328P-AU with its own +5V and GND nets, which then has a 0.1uF ceramic for decoupling, before passing through a pair of 0R resistors to the main ground and power planes. I've then got an LED display driver (MAX7219) with the same design, but with 1uF and 10uF reservoir capacitors due to the higher current demands, again with 0R resistors connecting the nets to power and ground. I'm doing the same again for an ESP8266 module.
My design isn't particularly sensitive and isn't going in an environment where people care about RF noise (aside from legal requirements), but I'm trying to be as careful as possible because any maintenance work on them is going to be near impossible after deployment, and I don't want them glitching out. The supply itself is expected to be fairly clean and I'm driving everything off a DI ATP1509-50 buck regulator.
Is this a sensible approach? Are there any guidelines for good practice on when/how to split power and ground nets like this?