# How to get the most significant bit being one in VHDL?

Say in VHDL I have an entity with as input a 8-bit vector:

libary ieee;
use ieee.std_logic_1164.all;

entity example is
port(
clk : in std_logic;
inputvector : in std_logic_vector(7 downto 0);
outputvector : out std_logic_vector(2 downto 0)
);
end entity example;


I want to output the position of the most significant bit being one in the input vector (starting with counting from zero).

So for example if $\text{inputvector} = [\underset{7}0,\underset{6}0,\underset{5}1,\underset{4}0,\underset{3}1,\underset{2}1,\underset{1}0,\underset{0}1]$, the most significant bit being one is bit $5$. And since $(5)_{\text{decimal}} = (101)_\text{binary}$, the output must be $\text{outputvector} = [1, 0,1]$.

What do I need to write in the architecture of example to achieve this?

Edit: How I would do this in Matlab or Python (with from numpy import ceil, log2):

ceil(log2(x)) - 1


with x the inputvalue. So $x = (101101)_\text{binary} = (45)_\text{decimal}$ would give

>> ceil(log2(45)) - 1

ans =

5

• I can only sugget to a switch statement where you check the value of each bit starting from 7 downto 0 – Engine Nov 28 '16 at 9:29
• If you have the space, a 256-entry LUT is the fastest way to do this. – Ignacio Vazquez-Abrams Nov 28 '16 at 9:30
• I would use an 8-bit shift register shifting to the left until you get your '1' and outputting a 3-bit counter incremented each clock cycle – A. Kieffer Nov 28 '16 at 9:37

Looking at that example, you would replace switch with your input, and assign your output using highest_switch.