2
\$\begingroup\$

I have a FSK modulated signal of binary data. This I am trying to recover using PLL.

The mark and space frequencies are in the range of 1.5MHz to 7MHz.

I am struggling because, the PLL output is not stable, in the sense that the signal is varying like a sine wave and this makes the decision process difficult (Because I am not able to fix the threshold as "0" or some other value).

Here is the PLL LPF output:

enter image description here

I know I cant use this directly for decision making so I am using a low pass equiripple filter after PLL, which gives a pretty good signal which I can use it for decision making. But again the probelm is the signal is varying like a sine wave and not proper horizontal variation, which is what I am looking for.

Here how the LPF output is:

enter image description here

All I want is that, to keep the center of the signal "0" at all time instant. How can I achieve that with simulink?

Here are the PLL, block parameters:

Filter: [1]/[1   2*pi*0.001]
VCO input sensitivity: 5 Hz/V
VCO Quiescent frequency: 10000 Hz
VCO initial Phase: 0
VCO output amplitude: 10V

Important Note: I am looking for demodulation at different data rates, so I want to vary from sample time in Bernoulli binary generator from 1 to 0.00001 i,e from 1bps to 100kbps. What I have observed here is that as the data rate changes, the property of the PLL filter output changes and which makes me to readjust the PLL for every significant change in this sample time (or as I referred it as data rate). For this if someone can give me tips or solution to demodulate the signal at every rate without re-adjusting the PLL, then it will be a lot of help.

\$\endgroup\$
  • 1
    \$\begingroup\$ No, you can post a picture of the block diagram. Unzipping a link is going too far. Curious, VCO senstivity 5Hz/v, and frequencies of 7MHz? That's over 1MV on the VCO, so I presume this is all in simulation? Unstable PLLs are generally naff loop filter design, so a diagram of the PSD, loop filter and VCO may be sufficient. \$\endgroup\$ – Neil_UK Nov 28 '16 at 12:31
  • \$\begingroup\$ How about adding in a high pass filter that will remove the sine wave portion? \$\endgroup\$ – KalleMP Nov 28 '16 at 12:39
  • \$\begingroup\$ Dear @Neil_UK...Thanks for the answer. The sensitivity at 5Hz/V did not differ the output from a sensitivity of 1MHz. Considering that my input modulating frequency components at 1.5MHz and 2.5MHz, in this example. I dont know why there was no significant different, but it is what I am observing. I am not expert, I am did all kind of trial and error methods but couldn't get the proper result. \$\endgroup\$ – gocjack Nov 28 '16 at 12:41
2
\$\begingroup\$

Well, if you can stabilize the PLL a bit more this is going to provide better pay-back when it comes to recovering the data but, in the absense of any improvement, you could try passing the signal through a high pass filter that has a cut-off close to the data rate frequency.

It should remove the lower frequency up-and-down wobble (to a large extent) but will tend to turn your data into edges like this: -

enter image description here

And, to recover the "differentiated data you could use a comparator with significant hysteresis or use two thresholds (either side of 0 volts) that set and reset a flip-flop. You could even low pass filter the data signal to make a signal that tends to follow the undulations (coming by the PLL) and use this to modify the thresholds to counter any undulations remaining after high pass filtering.

I've had to do pretty much that same on one job I was involved with and was very happy with the results. The amount of undulation superimposed on the signal was very similar to your example but, I would certainly start by trying to improve the PLL because any gains in removing the unwanted undulation makes life easier on the detect (data slicer) circuit.

Following on from the edit in the question I have a couple of observations about the PLL parameters: -

  • I think that your VCO quiescent frequency should be about 3 MHz and not 1 Hz
  • Given that the PLL output is up to 10 volts I think the VCO sensitivity is OK at 1 MHz per volt providing you make the centre (quiescent) frequency as I suggested.

What I have observed here is that as the data rate changes, the property of the PLL filter output changes and which makes me to readjust the PLL for every significant change in this sample time

When your data rate slows down and heads towards the low-pass frequency of the PLL loop filter you might get problems that are dependent on your application. Some applications allow the PLL VCO to track the modulated frequency (a fast loop filter) whilst other designs will want to keep the VCO at roughly half way between the two FSK frequencies (slow loop filter). It's unclear as to what your design is.

\$\endgroup\$
  • \$\begingroup\$ Thanks. The high pass filter seems to work. Now the signal is varying around "0" and not changing the course like a sine wave, I will update the final result once the complete simulation is done. \$\endgroup\$ – gocjack Nov 28 '16 at 12:54
  • \$\begingroup\$ But can you please elaborate a bit on how can we achieve this undulation handling with just the PLL itself ? taking my example into consideration. [This PLL then a low pass filter then a high pass filter just increases the cost if I have to implement a prototype lab experiment] \$\endgroup\$ – gocjack Nov 28 '16 at 12:56
  • \$\begingroup\$ I've added a couple of observations to my answer but making the centre frequency more like 3 MHz does seem to be logical. Also, can you explain what the low-pass numerator and denominator values represent. A more detailed block diagram of the PLL itself would be useful. \$\endgroup\$ – Andy aka Nov 28 '16 at 12:59
  • \$\begingroup\$ I tested for 3MHz and 1MHz VCO quiescent frequency, and also kept the VCO sensitivity at 1MHz, but then the PLL filter output will be ever increasing with amplitude for every bit change in the input signal (Leaving "0" and going away from it). \$\endgroup\$ – gocjack Nov 28 '16 at 13:10
  • \$\begingroup\$ And for the high pass filter, it works when the PLL filter output is around 0, but the moment the PLL filter output falls below 0, the detection fails. \$\endgroup\$ – gocjack Nov 28 '16 at 13:11

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.