Clock generation using FPGA

Question

I am trying to use Spartan 3E kit to generate 50 MHz clock. The kit comes along with a 50 MHz crystal which I am trying to use.

So, I wrote a simple code to output the clock from the FPGA to the SMA connector. The code is as follows:

module clock (in_clock, out_clock);

input in_clock;
output out_clock;

wire in_clock;
reg out_clock;

always @in_clock
out_clock = in_clock;

endmodule

The UCF file which mentions the pin configuration is as follows:

NET "in_clock" LOC = C9;
NET "out_clock" LOC = A10;

The output waveform of the 50 MHz clock looks like the following. The waveform is of 50 MHz but I do not get square pulses. In addition to that, the voltage level is too small (<10 mV). Can someone please tell me where the problem could be? 50 MHz clock http://www.ee.iitb.ac.in/student/~neelsmehta/2012-02-23%2011.08.20.jpg

Answer 1

The 50 MHz clock input should be on pin D9, not C9. You should double check this, as I could be reading the schematics wrong and assuming too many things that you left out of your question.

IF your signal amplitude were close to 3.3v then the not-so-square square-wave would be the result of how you are terminating your signal (probably no termination) and bad o-scope measurement techniques. But since your "signal" is only 10 mV, I think there are other issues.

I should also mention that I don't know Verilog, so I'm assuming that your Verilog code is good. I'm more of a VHDL person...

So, my best guess at what is going wrong is this... You have your clock input on the wrong pin. Your scope probe is on the correct signal, but there is nothing there. You're seeing a 50 MHz signal on the o-scope because of crosstalk and other noise effects and this signal is not actually being output from the FPGA.

Answer 2

This is coming a bit late, but one thing that would explain getting only 10 mV output is if JP9 has no jumper loaded. That would mean that there's no board-level connection to power for the IO buffers that should be driving this output, and you'd nominally expect no output at all.

But its possible there's a parasitic path to those drivers' power supply from some other power input, or just signal leak-through through the un-powered circuits, allowing you to see the very small output signal.

Answer 3

This doesn't answer your question, but to follow up on David's answer, you can simplify your code significantly:

module clock (in_clock, out_clock);

input in_clock;
output out_clock;

assign out_clock = in_clock;

endmodule

• It's not necessary to declare an input as wire or reg, because it can never be a reg.

• out_clock is better implemented as a wire than a reg, since you're implementing it with combinatorial logic. The only case I know where combinatorial logic is commonly expressed with an always block is to generate a multiplexer.

• There's no need to explicitly declare a port net as a wire, because that's the default.

I believe that what you wrote should also give the same behavior as this code, but it would be worth trying out the simpler form, because synthesis tools work by recognizing common patterns in your code, so if express your design in an "unusual" way, its possible to confuse the synthesis tool. In this case, it might see your always block and attempt to implement a latch or flip-flop. Which would result in incorrect logic for your design.

Answer 4

The input impedance needs to be 1 Mohm and not 50 ohm.