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I am designing a PCB with High speed video interfaces and I would like to know the way to calculate the maximum tolerance that I can count on while I am length matching all the traces.

When I routed the signals from the DVI driver chip to the connector, there where guidelines all over the internet, but when I am trying to route the bus from the driver chip to the FPGA, it is not that easy to find a guide like that.

So all in all the question is:

I have a bus with a frequency up to 165MHz with 24 signal traces. I would like to know the tolerances that I can count on while I am length matching these traces. I would like also to know how to calculate that.

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    \$\begingroup\$ Which chip driver are you using? What time skew does it allow in the input lines? A quick answer, the maximum track length difference is based on the maximum timing skew allowed in the signals considering the speed of travelling of the signals over the tracks. \$\endgroup\$ – Jesus Castane Nov 29 '16 at 10:15
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Jesus' comment is right, you need to look into your FPGA's and driver's datasheet to learn how much skew is admissible.

For 165 MHz signals, it's not unlikely that the signal is actually transported as low-voltage differential signal – thus, a single signal is not a single trace, but a pair of traces, which need to be more tightly matched. Rule of thumb says 10° – how much trace length difference that is depends on your trace design, PCB substrate thickness and material.

Many FPGAs do have some feature they call "IO delay calibration" or similar, which allows, within boundaries, to add an adjustable delay to IO lines.

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