I've managed to solve this problem but before I post the solution, just wanted to note a few things, namely:
- You cannot have a signal that's sensitive to two clocks. That's why you cannot react to presses of
key(1) at the same time.
- You cannot detect both a rising and falling edge of a signal. That's why, even if you merge both key presses into a
signal bit, you still wouldn't be able to do much with it.
- The solution presented by @Andrew doesn't work because it's built on unsafe assumptions. If you put it into hardware, the buttons will respond intermittently (unreliably). Which is easily explained by the fact that processes are concurrent in VHDL.
So now, the real solution. What we do is introduce two signals that indicate the number of times each button was pressed:
signal up, down : integer := 0;
Then, we simply assign these signals at each button press:
if (key(0)'event and key(0) = '0') then
up <= up + 1;
if (key(1)'event and key(1) = '0') then
down <= down + 1;
And then, at the architecture level, we simply put:
setting.temp <= up - down;
If you want to nitpick, this solution doesn't handle overflow (button pressed > 2^31 times) but that's not a real problem.