I'm using a freescale PowerPC microcontroller. In the flash memory module in the datasheet, the number of "wait states of the flash memory access" is configurable.
The following is the part of the datasheet raised my question, it's taken from the register description of the PFlash module registers :
This field must be set to a value corresponding to the operating frequency of the PFlash and the actual read access time of the PFlash. Higher operating frequencies require non-zero settings for this field for proper Flash operation.
0 MHz, < 23 MHz, wait states required = 0 ---
23 MHz, < 45 MHz, wait states required = 1 ---
45 MHz, < 68 MHz, wait states required = 2 ---
68 MHz, < 90 MHz, wait states required = 3 ---
(PFlash is Platform Flash controller module)
I understand that the processor is faster than the flash, that's why wait states are introduced. What I don't understand, is : if processor is faster than flash, then the processor is the one that needs to be slowed down not the flash, but the paragraph above says the opposite (or did I not understand this?), it says that in case the Pflash is operated with high frequencies, then we need to slow it down by adding to it additional wait states !!
What's wrong with my understanding ?