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Is it a bad idea to draw a polygon locally on the top side of two sided PCB as an alternative to proper solid power plane and star routing and place decoupling capacitors like this:

Close up board view showing the IC and the decoupling cap

This is how my board looks now. Main 3.3V power net is highlighted. Small polygon on the bottom layer right in the middle is local 1V power plane. Top-right IC is 1V linear regulator. Large thermal pad should be stitched with ground plane. Please don't pay attention to vias close to power pads.

Full PCB, power routes highlighted (ground plane hidden)

Both ground planes are filled:

Full PCB, power routes highlighted (ground plane shown)

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    \$\begingroup\$ The trick is to have a short (i.e. low impedance) path from VCC to GND, maybe have the grounds of the decoupling caps pointing more towards the chip, it's the loop area that's important, but below a few 10s of MHz, the placement starts to get pretty forgiving anyway. Or, failing that, have the caps underneath, that's the most common way I've seen of decoupling large high-speed ICs. \$\endgroup\$ – Sam Nov 30 '16 at 22:18
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As others have mentioned it's important to place the decoupling capacitors as close to the IC pins as possible to minimize the trace inductance between the capacitor and the IC supply pins. Otherwise it defeats the purpose of the decoupling capacitor. Power pours are a great way to make connections and are perfectly acceptable in your case.

It's important, however, that the supply voltage "hits" the capacitor first and THEN goes to the IC. In other words, you should not have the power plane connect directly to the IC supply pins using thermals. Instead, have it connect to the capacitor using thermals and then have a discrete trace connecting the capacitor to the pin. So instead of your first picture, on all IC connections to decoupling capacitors you should use something like this:

enter image description here

Notice that this way the capacitor is "hit" first before the power can get to the IC pin. In your original image you have the pour "hitting" the IC pin directly, and the capacitor will be of little use.

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  • \$\begingroup\$ It can be done using small rectangles on top restrict layer in between the IC pin and capacitor's power pad to prevent creating thermals there. \$\endgroup\$ – e_asphyx Dec 1 '16 at 13:56
  • \$\begingroup\$ Yes, that is certainly a way to do it. You may also be able to mess around with the polygon pour rules (I know you can do this in Altium, not sure how much freedom Eagle gives you) but polygon cutouts are definitely one of the easiest ways to do that. \$\endgroup\$ – DerStrom8 Dec 1 '16 at 15:04
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There is nothing wrong with a power plane on top layer and locally to a specific chip as long as you achieve a low impedance PDN (Power Distribution Network) i.e. a low impedance path for all your power rails.

The general rule for this is placing decoupling capacitors as close as possible to the IC power pins, as you have already done. Then, connect these decoupling capacitors to the power planes (Vcc and GND) with a solid connection, it may need a via.

This should be enough for a circuit like this.

You did well when you routed first the 1V plane. Now, you can route the 3V plane around this 1V plane. If you need, route part of the 3.3V power rail on top layer.

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  • \$\begingroup\$ That is how it was done on reference design for this IC. But reference design was done on 4 layer board. In my case it will leave large hole in the ground plane. \$\endgroup\$ – e_asphyx Dec 1 '16 at 14:09

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