Can you show me how to implement it? I tried many times, but I still couldn't get it done.
OK, sure, why not? I've got nothing better to do for the next half hour.
Let's define the functionality. Each read port comprises an address input and a data output. Each write port comprises an address input, a data input and a "write strobe" input. We'll give write port A permanent priority over write port B for simplicity — if they both try to write to the same register, it will be A's data that prevails, and B's data will be discarded.
simulate this circuit – Schematic created using CircuitLab
I've shown the data paths as just one bit wide, but the design is the same for wider buses; the input and output muxes as well as the registers just need to be wider.