Consider the following 6-layer stack-up for a mixed signal board.

 1: Top --- analog signals, components ---------------
    ================================================== (0.20 mm)
 2: GND --- return path for analog signals -----------
    ================================================== (0.36 mm)
 3: Pwr --- supply 1, supply 2, supply 3 -------------
    ================================================== (0.28 mm)
 4: Sig --- high-speed digital signals ---------------
    ================================================== (0.36 mm)
 5: GND --- return path for high-speed signals ??? ---
    ================================================== (0.20 mm)
 6: Bot --- control signals --------------------------

Layer 2 and 5 are solid ground planes, without splits in the copper. Layer 3, the power plane is split up into several regions (AVDD, DVDD, VCLK).

What I am trying to achieve, is to keep the layer 2 GND "clean".

My guess is that the high-speed return current should flow trough layer 5. Since this plane is directly underneath the high-speed signal trace, it should offer the lowest impedance return path. Am I right? Does this stack-up make sense at all?

  • 1
    \$\begingroup\$ What are the thicknesses of the dielectric layers between the copper layers? \$\endgroup\$ – The Photon Dec 1 '16 at 0:08
  • \$\begingroup\$ Why do you have high-speed digital signals running under analog circuitry to begin with? \$\endgroup\$ – ThreePhaseEel Dec 1 '16 at 23:22
  • \$\begingroup\$ @ThreePhaseEel My naive motivation is as follows: 1) The high-speed digital signals are running on an inner layer to increase immunity and reduce emissions. 2) The high-speed digital signals are shielded from the analog signals by ground planes. \$\endgroup\$ – sergej Dec 2 '16 at 8:12
  • \$\begingroup\$ I mean -- why aren't your high-speed digital parts confined to one area of the board, where their signals don't ever mix with the analog signals? \$\endgroup\$ – ThreePhaseEel Dec 2 '16 at 12:36
  • 1
    \$\begingroup\$ The possible problem is that the distance to layer 3 is smaller, so current will "prefer" to return on layer 3 instead of 5. If there is a gap on this layer (because it's a split plane) near the traces on layer 4, that will affect SI and also generate EMI. \$\endgroup\$ – The Photon Dec 6 '16 at 16:59

In this design, the return current of high speed digital signals in layer 4 will be almost equally distributed between layers 3 and 5. This is OK until layer 3 has no discontinuities (isolation gaps) along any of digital lines. Careful routing may help to achieve this goal. Then your planes 1 and 2 stay "clean" of digital signals.

If you can not avoid gaps in layer 3 across the digital lines, you have to place them in Bottom layer.

  • \$\begingroup\$ There is a exhaustive answer to this electronics.stackexchange.com/questions/14262/… \$\endgroup\$ – Janka Dec 1 '16 at 21:57
  • \$\begingroup\$ "between layers 3 and 5" ? Do you mean "2 and 5". Layer 3 is a split power plane. \$\endgroup\$ – sergej Dec 2 '16 at 7:54
  • \$\begingroup\$ There is no mistake. The return current is equally split between two neighboring layers. They are: 3 and 5. \$\endgroup\$ – Master Dec 2 '16 at 14:37
  • \$\begingroup\$ But 3 is a power plane, shouldn't the return current flow through the ground planes only? \$\endgroup\$ – sergej Dec 2 '16 at 15:45
  • 1
    \$\begingroup\$ There is no difference between ground planes and power planes, particularly for AC high frequency return currents. You call planes "GND" or "Power", but AC current only see the copper it can flow. It does not know names. \$\endgroup\$ – Master Dec 4 '16 at 8:07

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