# High speed signal return path in a stack-up with multiple ground planes

Consider the following 6-layer stack-up for a mixed signal board.

 1: Top --- analog signals, components ---------------
================================================== (0.20 mm)
2: GND --- return path for analog signals -----------
================================================== (0.36 mm)
3: Pwr --- supply 1, supply 2, supply 3 -------------
================================================== (0.28 mm)
4: Sig --- high-speed digital signals ---------------
================================================== (0.36 mm)
5: GND --- return path for high-speed signals ??? ---
================================================== (0.20 mm)
6: Bot --- control signals --------------------------


Layer 2 and 5 are solid ground planes, without splits in the copper. Layer 3, the power plane is split up into several regions (AVDD, DVDD, VCLK).

What I am trying to achieve, is to keep the layer 2 GND "clean".

My guess is that the high-speed return current should flow trough layer 5. Since this plane is directly underneath the high-speed signal trace, it should offer the lowest impedance return path. Am I right? Does this stack-up make sense at all?

• What are the thicknesses of the dielectric layers between the copper layers? Commented Dec 1, 2016 at 0:08
• Why do you have high-speed digital signals running under analog circuitry to begin with? Commented Dec 1, 2016 at 23:22
• @ThreePhaseEel My naive motivation is as follows: 1) The high-speed digital signals are running on an inner layer to increase immunity and reduce emissions. 2) The high-speed digital signals are shielded from the analog signals by ground planes. Commented Dec 2, 2016 at 8:12
• I mean -- why aren't your high-speed digital parts confined to one area of the board, where their signals don't ever mix with the analog signals? Commented Dec 2, 2016 at 12:36
• The possible problem is that the distance to layer 3 is smaller, so current will "prefer" to return on layer 3 instead of 5. If there is a gap on this layer (because it's a split plane) near the traces on layer 4, that will affect SI and also generate EMI. Commented Dec 6, 2016 at 16:59