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I have a question asking to draw a circuit for a NAND gate with one nMOS and one pMOS. The way the question is it sounds like it means only one of each. I know you can do that gate type with two nMOS each to an input betwen ground and vdd so if both inputs are "1" the bothe gates are open and the path is open, and Ive seen a version with two pMOS between vdd and the output, but I dont see any way to di it with just one of each. Is this posible, are am i taking the meaning of the question wrong?

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  • \$\begingroup\$ Go look at application notes on analog switches \$\endgroup\$ – Voltage Spike Dec 1 '16 at 0:19
  • \$\begingroup\$ you can also share the actual question \$\endgroup\$ – User323693 Dec 1 '16 at 6:44
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There are a implementations using "pass-transistor logic". They don't regenerate the logic levels, so they should be mixed with regular CMOS logic.

Google gives a number of different results, one of them:

enter image description here

Update: as noted by Ken Shirriff this implementation shows an AND-gate. A NAND implementation is shown below, but again inverters are required.

enter image description here

(Source: A general method in synthesis of pass-transistor circuits)

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  • \$\begingroup\$ I hate to point out that the question is for NAND but the answer provides AND. \$\endgroup\$ – Ken Shirriff Jan 3 '17 at 12:43
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NAND GATE

NAND gate can be done with two PMOS AND two NMOS. One possible implementation as seen on the image.

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