I have a question asking to draw a circuit for a NAND gate with one nMOS and one pMOS. The way the question is it sounds like it means only one of each. I know you can do that gate type with two nMOS each to an input betwen ground and vdd so if both inputs are "1" the bothe gates are open and the path is open, and Ive seen a version with two pMOS between vdd and the output, but I dont see any way to di it with just one of each. Is this posible, are am i taking the meaning of the question wrong?
There are a implementations using "pass-transistor logic". They don't regenerate the logic levels, so they should be mixed with regular CMOS logic.
Google gives a number of different results, one of them:
Update: as noted by Ken Shirriff this implementation shows an AND-gate. A NAND implementation is shown below, but again inverters are required.