How does a 40 Gbit/s Ethernet interface process packets in silicon?

A 40 Gbit/s Ethernet interface should have a 40 GHz signal on it. How does common silicon IC technology handle such an exotic beast?

My best guess is that internally various parallel busses are used, but I haven't found much on the internals of these things.

• you don't need 40GHz signal to transfer 40 billion bits, because you can send multiple bits in a clock cycle. For example by differentiating more voltage levels (like in SSD TLC, MLC...) or transmitting multiple times in a clock by pumping Dec 5, 2016 at 9:57
• Or by transmitting on multiple parallel wires. Dec 5, 2016 at 21:16
• or if analog is included, multiple frequencies+phases, etc... Dec 6, 2016 at 15:20

There are several ways how you can make a data link faster:

• make more transmissions per second
• send more bits per transmission
• run several links in parallel

40G Ethernet does all of this: according to Wikipedia, it uses 4 channels, running at 1.6GHz each and transmitting 6.25 bits per clock cycle, which results in 40Gbit/s of total bandwidth.

Here's a picture that shows you how it relates to other Ethernet technologies (it stops at 10G; 40G uses better cables and/or shorter distances to achieve 4 times the spectral bandwidth):

• How is "bits per hertz" the unit? Shouldn't that be "bits per cycle" or "bits-per-second per hertz"? Dec 6, 2016 at 0:32
• @R.. The unit should be just "bits". Hz is 1/s, so #channels * bits * spectral bandwidth is [1]*[b]/[s], which is a speed. Bits per second per hertz is [b]/[s]/[1/s] = [b][s]/[s] = [b]. Dec 6, 2016 at 4:47
• Well it depends on if you consider cycles a "unit" or a unit-less count. But yeah. Dec 6, 2016 at 5:04
• @R.. I replace "bits per hertz" with "bits per sample", which is indeed more accurate. Dec 6, 2016 at 11:07
• That graphic is gorgeous :) Dec 6, 2016 at 12:48

40G Ethernet is really four physical 10G links running in parallel. Modern FPGAs have SERDES hardware that can run at well over 10 Gbps, and it's common to use four 32-bit buses running at 312.5 MHz inside the FPGA. That gives you a data rate of exactly 40.000 Gbps.

• ...and 10G links will not actually be carrying a 10GHz RF signal, common 10G ethernet standards are meant to work on cabling specified to 250MHz. The bandwith is from using appropriate modulation schemes... How the demodulator distributes the recovered information "into the rest of the IC" is up to the designer.... Dec 5, 2016 at 9:03
• @JayKeegan The Shannon-Hartley theorem says you can do that if you have an SNR of 2^40 - 1, which is about 120dB. Dec 5, 2016 at 21:19
• 10G copper connections distribute the bandwidth over all four pairs in the cable, so each pair only handles 10 bits/Hz, requiring about 30 dB SNR. A 40G copper connection (4 cables) is therefore using 16 physical pairs of wires. Dec 5, 2016 at 21:51
• A simplistic example of Hz != Bps: if you can distinguish at 1 V increments between 0 V and 7 V, a 100 Hz signal can send log2(8) * 100 = 300 Bps Dec 6, 2016 at 0:46
• @JayKeegan You're probably thinking right now of a modulation scheme called ASK (Transmitting = 1, Not Transmitting = 0) or BPSK (Phase 0 degrees = 0, Phase 180 degrees = 1). But those are not the only modulation schemes. For instance, you could theoretically transmit infinite bits of information down a noiseless channel simply by sending a signal with a very precise DC voltage or AC voltage down the line and reading it very precisely at the other end. The same could also be done using a signal with a very precise frequency or phase. The reason you can't do this is of course noise. Dec 6, 2016 at 4:09

Check out the IEEE red-rag, the Journal of Solid State Circuits, in the library. Almost every issue has 40GigaBit receiver discussions.